| 3893d79d | 06-May-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: Add support for bridge chain
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Change-Id: Ie903996f919b6ac9b8103873bafd9b6adae5d7be |
| 97273498 | 27-May-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: phy-rockchip-samsung-hdptx-hdmi: Set bus_width before dclk enable
Fix 10bit pll cfg error.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: Ie88701a7fbfe6d9267685d8238a656b
video/drm: phy-rockchip-samsung-hdptx-hdmi: Set bus_width before dclk enable
Fix 10bit pll cfg error.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: Ie88701a7fbfe6d9267685d8238a656bed12d57d3
show more ...
|
| 8ae84ec5 | 19-May-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: Add AUX channel detect
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Change-Id: I104a342aa8e681d4b17ef759a30e542f62b52d57 |
| cebdc49b | 11-May-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Workaround for FRL mode no signal after plug
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: I8be564981f25c8854c9870c8d0599ba06c88976f |
| e72a3bee | 10-May-2022 |
Guochun Huang <hero.huang@rock-chips.com> |
video/drm: dsi2: use mode->crtc_clock instead of mode->clock to calculate
Change-Id: I026639eff059a66ab9deee913053dda1b03c0812 Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> |
| 79ddcdb6 | 10-May-2022 |
Guochun Huang <hero.huang@rock-chips.com> |
video/drm: dsi2: support specified lane rate by rockchip,lane-rate in Mbps/Kbps
Change-Id: I0cebc7a89b8e88fa463d44e41d80376faabac3be Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> |
| 63638f32 | 07-May-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop2: get actual allocated mode->crtc_clock
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: Ib0f5147cb2c518b4f779988de65c6d7e81bee4e7 |
| caf17927 | 30-Apr-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: dsi2: get pps data and set to connector_state
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> Change-Id: I594b7e90f1acb3ddf9
video/drm: dsi2: get pps data and set to connector_state
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> Change-Id: I594b7e90f1acb3ddf9247ae08df721224d6a4b2a
show more ...
|
| 12ee5af0 | 05-May-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop2: add support for dsc
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: Id9018e0c7eaeabb74cd49c834bb079070e43658a |
| b6ba80b4 | 28-Apr-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop2: add dsc pd_data and modify pd_on function
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: I82f1203870abe44f721b12e0e7863b788735b165 |
| e22c03ed | 29-Nov-2021 |
Guochun Huang <hero.huang@rock-chips.com> |
video/drm: panel: add support dsc/pps sequence transfer for dsi
Change-Id: I455e551770db2c577c2103df90289aad69fba7cd Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> |
| a92bdacc | 29-Nov-2021 |
Guochun Huang <hero.huang@rock-chips.com> |
video/drm: dsi: add dsc helper
Change-Id: I06792d0977d1a72ba35966f5b6a8f5b55e884fcd Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> |
| cbfcaedb | 29-Nov-2021 |
Guochun Huang <hero.huang@rock-chips.com> |
drm/dsc: Add helpers for DSC
Change-Id: I32bbc9ab9650f62fc67e4ebb1c5051c5a62ed69a Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> |
| ee01dbb2 | 19-Apr-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop2: add support for 8k display
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: I6901a589a0acfe370c00ab6b7038e8536abc1ea9 |
| 631ee99a | 12-Apr-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
drm/rockchip: vop2: constraint the hdmi phy pll using condition
only when the dclk rate uder 600 MHz, the hdmi phy pll can be used.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com> Change-
drm/rockchip: vop2: constraint the hdmi phy pll using condition
only when the dclk rate uder 600 MHz, the hdmi phy pll can be used.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com> Change-Id: I9be3fe76161a4139e884bf270e9b9a946c46cb19
show more ...
|
| 10d706d5 | 14-Apr-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: Fix link train adjust request
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Change-Id: Iadb6acf1be45e9e3f72d41a580f3a5fd8e6940f4 |
| 1848455f | 18-Apr-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop2: add edp1_en reg setting
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: I8387e32e4570f0a26bdbaa5edc7553e1f4797d3f |
| cd24009b | 09-Apr-2022 |
Guochun Huang <hero.huang@rock-chips.com> |
video/drm: phy: dcphy: use m_phy_rst to describe M_RESETN
M_RESETN: reset to PLL、TX Clock lane and data lane 0/1/2/3 block
Change-Id: I532c68361de19d88afefe701692030a284146c57 Signed-off-by: Guochu
video/drm: phy: dcphy: use m_phy_rst to describe M_RESETN
M_RESETN: reset to PLL、TX Clock lane and data lane 0/1/2/3 block
Change-Id: I532c68361de19d88afefe701692030a284146c57 Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
show more ...
|
| f721bd04 | 30-Mar-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop: add more supported yuv bus formats
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: Ie8200276d3e5b9bd64684c68f6083740cff12c3d |
| 5efdd3e2 | 09-Mar-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
video/drm: dw-dp: support force output without connect dp device
When config force output, It need output image data though no dp device connect.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chip
video/drm: dw-dp: support force output without connect dp device
When config force output, It need output image data though no dp device connect.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com> Change-Id: I2df13cf171dbac4ba96f730a4142f727895646a5
show more ...
|
| c1035eae | 17-Mar-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: phy-rockchip-samsung-hdptx-hdmi: Add PLL setting calculation
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Change-Id: I9f737fdd9f15e28e37d6f7f3976ed14396b00545 |
| e93ec37e | 16-Mar-2022 |
Andy Yan <andy.yan@rock-chips.com> |
Revert "drm/rockchip: vop2: disabled aclk of video port when unused"
This reverts commit 0b728e80d45136ed20e3e88ef5bda470c9076917.
According the test, this fuction is not stable.
Change-Id: Id4323
Revert "drm/rockchip: vop2: disabled aclk of video port when unused"
This reverts commit 0b728e80d45136ed20e3e88ef5bda470c9076917.
According the test, this fuction is not stable.
Change-Id: Id43238119edfe8eca7c373b341bdc427496d5691 Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
show more ...
|
| 12f57f38 | 12-Mar-2022 |
Guochun Huang <hero.huang@rock-chips.com> |
video/drm: phy: dcphy: accurately set mipi channel rate to Kbps/Ksps level
take 1280x720@60Hz which pclk is 74.25Mhz as an example, the dsi lane rate should set 445500 Kbps/lane(pclk x bpp = lane_ra
video/drm: phy: dcphy: accurately set mipi channel rate to Kbps/Ksps level
take 1280x720@60Hz which pclk is 74.25Mhz as an example, the dsi lane rate should set 445500 Kbps/lane(pclk x bpp = lane_rate x lanes) when mipi work in no video burst pulse/event, therefore the PLL should output the rate of Kbps/ksps level for normal display.
Change-Id: Iba0118517462aa71fd18fafc42a0b5c0c190334d Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
show more ...
|
| 7a63fd76 | 12-Mar-2022 |
Guochun Huang <hero.huang@rock-chips.com> |
video/drm: dsi2: accurately set mipi channel rate to Kbps/Ksps level
Change-Id: Ie87c00d1e2e84df73fe7363247a2dd4ae0f8e5e3 Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> |
| 4b4a41fb | 12-Mar-2022 |
Guochun Huang <hero.huang@rock-chips.com> |
video/drm: dsi2: make horizontal scanning setup time more accurate
Change-Id: I2705a76c7a659913b06aa8d2829d855988ec9978 Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> |