drm/rockchip: vop2: set reg merge_en only when vp is in splice mode

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I27d4e74880939181b17bb711ef9fc7155f830551

drm/rockchip: vop2: fix display error at fullscreen and 8k output

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I95cbd8c62baab630534a16913d2316b54ac0bdb9

drm/rockchip: display: fix logo_mode check error

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ieab8f6bb7fe57ed198f6086cedf0833c3616b66c

video/drm: dw-hdmi-qp: Send VSI once per frame

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I9626c80df27fc1d4899e382e478b1633bf06f574

video/drm: dw-hdmi-qp: Clear avmute when hdmi enable

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I7f4a0aec7f4995647c1ff17f9be9d251c2bd61b4

video/drm: dw-hdmi-qp: Set color depth and phase to 0 when 24-bit format

According to CTS requirements, CD field and PP field in GCP
should be set to zero when 24-bit output.

Signed-off-by: Algea C

video/drm: dw-hdmi-qp: Set color depth and phase to 0 when 24-bit format

According to CTS requirements, CD field and PP field in GCP
should be set to zero when 24-bit output.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I4557585360febc7863ddcfa7159e0063ca483d02

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video/drm: dw-hdmi-qp: Fix display err when reboot in hdr mode

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ida4aae89ca492c789ed94f9aaf864f64f546219f

video/drm: dw-hdmi-qp: Fix 8K30/25/24 YUV420 no enter FRL mode

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ifa4f87a718c7532c7affe0a6fe5897eac366d1a9

phy: phy-rockchip-samsung-hdptx: Increase the poll times of phy lock

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I05a1c515b7e59d0560f463dac3f82ab607c7cdaf

video/drm: dw-hdmi-qp: Set default color format as YUV444

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ida9a6f34ee28e8628e9bf939873430c14c6f52f9

video/drm: Kconfig: select PINCTRL_MAX96755F when enable CONFIG_DRM_MAXIM_MAX96755F

Change-Id: I8491bcf6dccc96553c6d5e9d0ef04f5073fa2e3a
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

video/drm: max96755f: Implement bridge detect

Change-Id: Ia94273aba33e94a48a0e126b5790ac4eb3d1abaa
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

video/drm: max96752f: Move max96752f_init() call to max96752f_bridge_pre_enable

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ia8be48eed63c3ecb6478e45ca52cb6ff04abaa9f

video/drm: max96745: Implement bridge detect

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ic183ea9178e7ede643edfe3ec0225c62620f2ff4

video/drm: Add support for bridge detect

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I5611c92de67efd474e41d63fe9eb81cf136b2821

video/drm: dw-dp: Add DP PHY max_link_rate limit

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I2fe8f4e8d7f9ec0b75db64122346390e8f0522ea

video/drm: BU18TL82-M/BU18RL82-M: print i2c access failure info

Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I4230f8e6b27330a16742873e18956e1286e25a72

drm/rockchip: vop2: fix some log description

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Iff85dbf142165384a8cecbbf0155fe2e1b9345ac

drm/rockchip: vop2: fix the calculation method of crtc clock

Fixes: 63638f3204 ("drm/rockchip: vop2: get actual allocated
mode->crtc_clock")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Cha

drm/rockchip: vop2: fix the calculation method of crtc clock

Fixes: 63638f3204 ("drm/rockchip: vop2: get actual allocated
mode->crtc_clock")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ie500f1c86a21ad05cd9dfe356d5fbd8c4ffee422

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video/drm: dsi2: add support attach bridge

Change-Id: Ieccc8302595191bca73d128f9dc4fd8d2f38ebea
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

video/drm: dw-hdmi-qp: Support VSI packet

1.Support 3d mode.
2.Support hdmi1.4 4K resolution VIC number.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: If5c673e861c5498a1759519b8b7b

video/drm: dw-hdmi-qp: Support VSI packet

1.Support 3d mode.
2.Support hdmi1.4 4K resolution VIC number.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: If5c673e861c5498a1759519b8b7b76d98d34370f

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video/drm: Add support for BU18TL82-M/BU18RL82-M

BU18TL82-M supports MIPI DSI and LVDS data
transmission by ROHM's original CDR (Clock Data
Recovery) technology. This chip is the serial interface
tr

video/drm: Add support for BU18TL82-M/BU18RL82-M

BU18TL82-M supports MIPI DSI and LVDS data
transmission by ROHM's original CDR (Clock Data
Recovery) technology. This chip is the serial interface
transmitter IC of the Clockless Link-BD series.

BU18TL82-M converts the MIPI DSI and LVDS data
stream into Clockless Link format transmit through 2
pairs of differential wires.

BU18RL82-M supports LVDS data transmission by
ROHM's original CDR (Clock Data Recovery) technology.
This chip is serial interface receiver IC of the Clockless
Link-BD series.

Change-Id: I0545eedcb4f76cebc56a59ab107eb24028ab71ce
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

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video/drm: phy-rockchip-samsung-hdptx-hdmi: Improve signal quality

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I3e750620dfc7fcf6fa463bb7dfe6371647e885c6

video/drm: dw-hdmi-qp: Configure YCC quant range and colorimetry correctly

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I9fb7143a69653ea0eb8acf6350156da077776353

video/drm: dw-hdmi-qp: Support avi version 3

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I79fdc8eb25f163f09ea2c72b4266f128b00cc331