| e8dd2b64 | 29-Jul-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: rgb: add support for rv1106
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I8b12bbbc64ad2eb1a26076e4cc6d1e17b1743e34 |
| 54f7137b | 18-Jul-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: vop: add support for rv1106
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I5bfdaaa7c37c4c528deac9e67fb217f565a9fe76 |
| 57c33e2a | 15-Sep-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: Fix sync polarity configuration in msa packet
Fixes: e9cac7f1fea9 ("video/drm: analogix_dp: Use video format information from register")
Signed-off-by: Wyon Bi <bivvy.bi@rock
video/drm: analogix_dp: Fix sync polarity configuration in msa packet
Fixes: e9cac7f1fea9 ("video/drm: analogix_dp: Use video format information from register")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I3cbf36d59976e460a852c16b039393311da69e18
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| 8c597bca | 05-Sep-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Optimize HDMI enable process
1.Support phy pll clk enable/disable is separated from
phy signal output.
2.To comply with the timing requirements of the HDMI protocol,
HDMI mu
video/drm: dw-hdmi-qp: Optimize HDMI enable process
1.Support phy pll clk enable/disable is separated from
phy signal output.
2.To comply with the timing requirements of the HDMI protocol,
HDMI must be enabled in tmds mode according to the following process:
disable FRL -> enable/disable scramble —> power up phy
3.Optimize flt process
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ia29337d7e82dfa09cef60447911f2fd2854bc89f
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| f037d38f | 05-Sep-2022 |
Algea Cao <algea.cao@rock-chips.com> |
phy: phy-rockchip-samsung-hdptx: Add function of enabling PLL independently in FRL mode
The phy pll must be enabled before access hdmi controller registers.
To support config hdmi controller registe
phy: phy-rockchip-samsung-hdptx: Add function of enabling PLL independently in FRL mode
The phy pll must be enabled before access hdmi controller registers.
To support config hdmi controller registers before phy output is
enabled, pll must be enabled separately in both TMDS and FRL mode.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I9eb7df9e4d6d989e0ff752bd9e1d8433aba1ffa4
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| 4c765862 | 05-Aug-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: display: add crtc plane check of scale factor
Check scale factor in vop/vop2 plane_check function.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Iaffbacb251a58825d7
drm/rockchip: display: add crtc plane check of scale factor
Check scale factor in vop/vop2 plane_check function.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Iaffbacb251a58825d7247da7f14d118c10b73bf8
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| 22007755 | 26-Jul-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: display: add display mode valid check
1.Filter out invalid display modes in vop/vop2
mode_valid function.
2.Reserve function of connector mode_valid check.
Signed-off-by: Damon Ding
drm/rockchip: display: add display mode valid check
1.Filter out invalid display modes in vop/vop2
mode_valid function.
2.Reserve function of connector mode_valid check.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Idc98b14d93c5abc2953b3d834e4842a727b91328
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| 2cb51333 | 25-Aug-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: add drm_display_mode to videomode conversion func
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I14eb31a2f36f5a34333beaaacd83ae7018d6cdd9 |
| 820a5c17 | 25-Jul-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: display: add display check
1. Add vop2 check function. Splice vp should not
be initialized in 8k mode.
2. Reserve function of connector check.
Signed-off-by: Damon Ding <damon.ding@ro
drm/rockchip: display: add display check
1. Add vop2 check function. Splice vp should not
be initialized in 8k mode.
2. Reserve function of connector check.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ib5ccf2201f72536ceb144bab6715b1d43d6e52fd
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| 1867b356 | 06-Aug-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: display: not to fixup dts if vp initialization fails
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I2d47198afd18fd2a75fa621b556ff45b856e3d92 |
| 77a9b3c7 | 05-Aug-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: Add panel driver for maxim deserializer panels
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: If8c969a1df6629de994f57aadb7ecb011b130c41 |
| 5e85f4a7 | 23-Aug-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
drm/rockchip: vop2: fix some log print
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I4fbc356c61e48174966ea2dfad829e8ad798cd91 |
| 43448503 | 23-Aug-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
video/drm: config some log in debug level
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I6d792813864b496f3baf1130720d4d1f8f620f96 |
| e14b9f0d | 23-Aug-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: Support max-link-rate property
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I28f3f49210d3e885bddc3b4fcd6184318ea4a0ed |
| 1d467516 | 22-Aug-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
Revert "video/drm: analogix_dp: Add AUX channel detect"
This reverts commit 8ae84ec538ac582ac1bcc85448e53b9f6de0e844.
Change-Id: Ibe2dc5c31d4e5ac95a2b3eb88a15b6745a97bfd4
Signed-off-by: Wyon Bi <bi
Revert "video/drm: analogix_dp: Add AUX channel detect"
This reverts commit 8ae84ec538ac582ac1bcc85448e53b9f6de0e844.
Change-Id: Ibe2dc5c31d4e5ac95a2b3eb88a15b6745a97bfd4
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
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| b752fb5d | 10-Aug-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: rockchip_panel: Add support for .get_mode callback
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ia95047eff7437ed86416b8cad2591885ce10e1cc |
| e022625e | 25-Aug-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: Add drm_modes.c
Sync from kernel 5.10:
drivers/gpu/drm/drm_modes.c
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I721de052bf66ac83483f02c2fe3101b56e6f1ff7 |
| ee32db20 | 25-Aug-2022 |
Luo Wei <lw@rock-chips.com> |
video/drm: rohm-bu18tl82/bu18rl82: reduce retry delay time
Signed-off-by: Luo Wei <lw@rock-chips.com>
Change-Id: Id749b3380eadee93c9a37841f9b7322bb5bf7e4b |
| 806b8544 | 08-Aug-2022 |
Luo Wei <lw@rock-chips.com> |
video/drm: rohm-bu18tl82/bu18rl82: improve init progress and add retry function if i2c failed
Signed-off-by: Luo Wei <lw@rock-chips.com>
Change-Id: Ia18bc6dc9706564ecbaca25f02c74cdc7348e7ae |
| 364352d1 | 29-Jun-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
video/drm: dw-dp: support split mode
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I922f98874a741d684b07c47c9f649ef71221eba8 |
| 0a1fb152 | 08-Jun-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
drm/rockchip: vop2: support split mode
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I372900c0b686398e3443ae2e7cc0c9971d817791 |
| ecf57f93 | 28-Jun-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
video/drm: support split mode
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I0b19a901731f2d8b9fdab931b79e9eda87a46b6b |
| 0594ce39 | 27-Jun-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
video/drm: support for multi connector
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Id87d4c81e60a9f69f3fbfc05ffd67a3d42cd21a4 |
| e9cac7f1 | 16-Jun-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: Use video format information from register
Force sync polarity to active low for RK3588.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I73270addc6118279accf6d9
video/drm: analogix_dp: Use video format information from register
Force sync polarity to active low for RK3588.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I73270addc6118279accf6d9ba01f3f018a4e0850
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| 9cf99b47 | 06-Aug-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: Fix TX lane count & rate setup
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I5724fb24fdf2c014c8eb642b9d4dbfb78db8af01 |