| aa670293 | 08-Dec-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: vop2: add dsp_vs_t_sel reg config
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: I773e1a21aadcd668fd70df84b3f208c66d4fb4b9 |
| 9764efeb | 14-Oct-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: display: add kernel logo valid check
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: Ic75aa73617497e8610a35a1fbf212eccf656c1cf |
| 38729a08 | 08-Dec-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: tve: modify tve and dac configs for SI
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: I53aa98ef922ac37c4076ee3f157c7a5c83f37d9c |
| 268b9134 | 02-Dec-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: Improve signal quality less than or equal to 340m
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: I95a2c2d908910ee74d9f609b160fe784c0a3f4e3 |
| baf2c414 | 08-Nov-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: vop2: modify config process of dsc_ctrl0 reg
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: Ia6ee748f43adcea7dd185e461915e0f9e68eb6b0 |
| 1ace1b6d | 10-Oct-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: vop2: update dsc_hsync and dly_num config
In addition, fix dsc_nslc mask and dsc clock calculation error.
Signed-off-by: Sandy Huang <hjc@rock-chips.com> Signed-off-by: Damon Ding <damon
video/drm: vop2: update dsc_hsync and dly_num config
In addition, fix dsc_nslc mask and dsc clock calculation error.
Signed-off-by: Sandy Huang <hjc@rock-chips.com> Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: I1892a0eeab7fadf292dc4f6b9e104ae45a79e54e
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| 4e8e620b | 30-Nov-2022 |
Chen Shunqing <csq@rock-chips.com> |
video/drm: phy-rockchip-samsung-hdptx-hdmi: solve the issue that memory is not freeed
Signed-off-by: Chen Shunqing <csq@rock-chips.com> Change-Id: Idccf20cb8f45488c98315076f2c02364f489334a |
| 84a9a3d8 | 30-Nov-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: Improve 594m signal quality
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: Id6c3ea9f1d44dd0c3490aecfd5821e21e4976fe9 |
| ebbd144c | 30-Nov-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: vop3: Add support for rk3528 hdmi
Support use inno hdmi phy pll as dclk source
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: I3bfd2f89df2fa4be3cfa871a2ce778871935b055 |
| cb24dc0e | 26-Nov-2022 |
Algea Cao <algea.cao@rock-chips.com> |
drm/rockchip: dw-hdmi: Add support for rk3528
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: I3ae3c428e5796f440e76d2ccbdda251a0fc66ecf |
| 19957ff8 | 08-Nov-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: Support rk3528 hdmi phy
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: Icd0b47b4592d7f7168400867ca272227aac8319d |
| 96f3d86b | 28-Nov-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: tve: fix the cvbs enable process
1. Config the vdac regs after bt656 decoder and tve regs. 2. Delay 1s between the two steps above, in order to ensure bt656 decoder and tve regs to tak
video/drm: tve: fix the cvbs enable process
1. Config the vdac regs after bt656 decoder and tve regs. 2. Delay 1s between the two steps above, in order to ensure bt656 decoder and tve regs to take effect.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: Ib9573719b9fa68bfd45cef29d323a4d29ae7c1b2
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| 7efea85d | 27-Nov-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: tve: four times the dclk for CVBS in rk3528
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: If5eb759fe57dd010aaf024ecbad44e7c15651ac4 |
| ffaa1c66 | 26-Oct-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: tve: rename rockchip_drm_tve to rockchip_tve
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: Ifa6fbf747b8a59d515a4d135ec77f8f50ffff491 |
| cf328f85 | 26-Oct-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: tve: add support for rk3528
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: I00e2c8f28bd5f55916fe1814169718d44389e681 |
| 5fa6e665 | 25-Oct-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: vop3: add support for rk3528
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: I7e238351be6d44c5a6cfdecf8201dc4c04862d04 |
| 337d1c13 | 25-Oct-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: vop2: init vp_primary_plane_order based on the soc
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: Icb6c69992d8f6741c9ef2be7536fde03c04c162b |
| db328a0d | 09-Sep-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: vop2: add gamma support for rk3588
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: I26edfc870bbbd8cf3d5ba4199103d63596e9045d |
| 40a4edb7 | 26-Sep-2022 |
Algea Cao <algea.cao@rock-chips.com> |
phy: phy-rockchip-samsung-hdptx: FRL 8Gbps * 4 lanes mode use pll cascade mode
Vendor suggest FRL 8G * 4 lanes mode use ROPLL/LCPLL cascade mode. ROPLL ref clock is from LCPLL.
Signed-off-by: Algea
phy: phy-rockchip-samsung-hdptx: FRL 8Gbps * 4 lanes mode use pll cascade mode
Vendor suggest FRL 8G * 4 lanes mode use ROPLL/LCPLL cascade mode. ROPLL ref clock is from LCPLL.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: I72ededdec20a87fc1a3245515bd09e902ee5cf58
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| 0d8f8624 | 26-Sep-2022 |
Algea Cao <algea.cao@rock-chips.com> |
phy: phy-rockchip-samsung-hdptx: LCPLL is also used for low rate frl mode
In RK3588C, 24M clock noise is carried into the PHY ROPLL loop filter. Due to the low noise frequency, it can pass through t
phy: phy-rockchip-samsung-hdptx: LCPLL is also used for low rate frl mode
In RK3588C, 24M clock noise is carried into the PHY ROPLL loop filter. Due to the low noise frequency, it can pass through the low-pass loop filter of ROPLL, resulting in hdmi clk jitter test fail. The loop bandwidth of LCPLL is low, so LCPLL can be used to circumvent this problem. RK3588 is also suitable for this scheme.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: Iadd87adfddd284937ae9b6ffe2d83595ea7c6fcc
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| 71ac76f7 | 28-Oct-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: display: fix crtc_rect calculation error
In crtc_rect calculation, vdisplay should not be crtc_vdisplay, which is halved in interlace mode.
Signed-off-by: Damon Ding <damon.ding@rock-chi
video/drm: display: fix crtc_rect calculation error
In crtc_rect calculation, vdisplay should not be crtc_vdisplay, which is halved in interlace mode.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: I88c2003ba817a75c487852a5c6a6dc1042664e8b
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| c7dcfb21 | 20-Oct-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
Revert "video/drm: analogix_dp: Fix sync polarity configuration in msa packet"
This reverts commit 57c33e2a3cb453933624c3769fe2f65158030c38.
VOP only supports the negative polarity of vsync/hsync o
Revert "video/drm: analogix_dp: Fix sync polarity configuration in msa packet"
This reverts commit 57c33e2a3cb453933624c3769fe2f65158030c38.
VOP only supports the negative polarity of vsync/hsync on rk3588.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Change-Id: If830138671b6a47bacbff0af7357457a974d5abd
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| ae5256b5 | 10-Oct-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: Fix stream valid control
Fixes: e9cac7f1fea9 ("video/drm: analogix_dp: Use video format information from register") Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Change-Id
video/drm: analogix_dp: Fix stream valid control
Fixes: e9cac7f1fea9 ("video/drm: analogix_dp: Use video format information from register") Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Change-Id: I94c32572bc8b58cc5902a1ada23f45f300d06ca5
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| c2b1fe35 | 05-Aug-2022 |
Damon Ding <damon.ding@rock-chips.com> |
video/drm: vop2: support to enable xmirror in dts
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: I41bb2700a51a8715f8581507f4c64fe066c87ff7 |
| 2afea1f0 | 15-Sep-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Support allm
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: I09ffdb392f6ef7f4513bf720ebba8382dad23b40 |