video/drm: display-serdes: add pin mux interface for rohm serdes

Signed-off-by: Luo Wei <lw@rock-chips.com>
Change-Id: Ifb7eeef70f50b2dc8e2e27cee74f2859c2d12c8d

video/drm: display-serdes: add serdes display driver support

* i2c register initialization with dts sequence from serdes chip vendor.
* pinctrl and gpio interface to operate the different serdes chi

video/drm: display-serdes: add serdes display driver support

* i2c register initialization with dts sequence from serdes chip vendor.
* pinctrl and gpio interface to operate the different serdes chips.
* bridge interface to transmit data for different ser chips.
* panel interface to drive lcds for different des chips.
* one ser chip to connect two des chips in order to costdown.
* support different serdes display chip such as maxim, rohm and rockchip.

Signed-off-by: Luo Wei <lw@rock-chips.com>
Change-Id: I97f6beecc86b58402a9e5971c11bacfe8014940e

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video/drm: dsi2: recalculate vfrefresh after modify mode

Change-Id: I170a730b87cba57290380b30931ac05a6e9ed511
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

video/drm: vop2: fix lvds data swap behavior

Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Change-Id: I7a677a69ac89fe407f7d6939a7bf8f9ed0c0496d

video/drm: lvds: add support for secondary lvds probe

Uses a method similar to the kernel to probe dual lvds.

Note that there is no defer mechanism in uboot, so these
operations need to be performe

video/drm: lvds: add support for secondary lvds probe

Uses a method similar to the kernel to probe dual lvds.

Note that there is no defer mechanism in uboot, so these
operations need to be performed when the first device is loaded.

The way of sharing data between the two connectors is
also different, but the overall operation is similar to the kernel.

Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Change-Id: I77dfff8dfe3cb37490b346fa6cd26cf189d08ae7

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video/drm: lvds: add support for dual lvds connector

There are two models of dual-lvds:
1. dual-channel-lvds: This mode has one panel with two separate
LVDS connector outputs for even and odd pixel.

video/drm: lvds: add support for dual lvds connector

There are two models of dual-lvds:
1. dual-channel-lvds: This mode has one panel with two separate
LVDS connector outputs for even and odd pixel.

2. dual-lvds: This mode has two panel, outputting the left content
and the right content respectively.

These two modes are regarded as the connectors in the split-mode,
just like dp/edp/hdmi.

In order to be consistent with the kernel, an additional DTS bool
attribute of "dual-channel" is added to help VOP determine whether
there are multiple LVDS connectors.

Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Change-Id: I1d3b3cfa20419db5fe089f89f8a3b91c40903e97

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video/drm: of: Add drm_of_lvds_get_dual_link_pixel_order

This patch is derived from the kernel and modifies parts of
it to support uboot dts API.

drm_of_lvds_get_dual_link_pixel_order supports the

video/drm: of: Add drm_of_lvds_get_dual_link_pixel_order

This patch is derived from the kernel and modifies parts of
it to support uboot dts API.

drm_of_lvds_get_dual_link_pixel_order supports the odd and
even channels which already present in the kernel as well
as the left and right channels specific to Rockchip SoCs.

Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Change-Id: I8b4d3d0367669c48ed6e8ea552faedb330f99b81

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video/drm: dw-hdmi-qp: add bridge support

Change-Id: Ib45235afcaaf126b4ee7856a5b37cbbeea9517d7
Signed-off-by: Chen Shunqing <csq@rock-chips.com>

video/drm: phy: dcphy: make Tskewcal maximum is 100 usec at initial calibration

Change-Id: I53c70f5108b2302ab5beed4b2dc9744ef730b913
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

drm/rockchip: dw-hdmi: Filter hdmi 2.1 resolution

Only rk3588 support hdmi 2.1

Change-Id: I4a94c9a914087a1c52d0add6b30511969501e2c9
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>

video/drm: vop: add debug logs about drm_display_mode

The added logs may be like:
......
VOP:0xff990000 update mode to: 320x480p45, type: RGB
VOP:0xff990000 set crtc_clock to 141120KHz
......

Signe

video/drm: vop: add debug logs about drm_display_mode

The added logs may be like:
......
VOP:0xff990000 update mode to: 320x480p45, type: RGB
VOP:0xff990000 set crtc_clock to 141120KHz
......

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ic4ca57a21d49d0f6167fb2fb7ae8d0ccf996c3d6

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video/drm: display: fix the dclk calculation of mcu interface

dclk = htotal * vtotal * frame-rate * cycles-per-pixel * (pix-total + 1)

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-I

video/drm: display: fix the dclk calculation of mcu interface

dclk = htotal * vtotal * frame-rate * cycles-per-pixel * (pix-total + 1)

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ia33d950b8df1129608dbf680dcf69d1baf2d169f

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video/drm: dsi2: havle dsc pps pic_width in dual channel dsi

<-HxV-> <------------- H/2 x V --------------> <-H x V->
┌───────┐ ┌───────┐ ┌───────────┐
│ DSC0 ├───►│dsi0

video/drm: dsi2: havle dsc pps pic_width in dual channel dsi

<-HxV-> <------------- H/2 x V --------------> <-H x V->
┌───────┐ ┌───────┐ ┌───────────┐
│ DSC0 ├───►│dsi0 tx├──►│lcd dsi0 rx│\ ┌───────┐
┌─────┐ /└───────┘ └───────┘ └───────────┘ \│ │
│ │/ /│lcd DSC│
│ VP │\ ┌───────┐ ┌───────┐ ┌───────────┐/ │ │
└─────┘ \│ DSC1 ├───►│dsi1 tx├──►│lcd dsi1 rx│ └───────┘
└───────┘ └───────┘ └───────────┘

Change-Id: I340a11627cff57464a4328cc2fe8e8557dfaefe8
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

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video/drm: dw-hdmi-qp: Add hdmi connector check

If hdmi bind to vp1 and it is 8K mode now, hdmi
logo display will be turned off and the hdmi logo
on flag must be cleared. Otherwise, it will cause
ke

video/drm: dw-hdmi-qp: Add hdmi connector check

If hdmi bind to vp1 and it is 8K mode now, hdmi
logo display will be turned off and the hdmi logo
on flag must be cleared. Otherwise, it will cause
kernel misjudgment.

Change-Id: I40ff7b5e4475886505f9fc3cc6f00e992cb68615
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>

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video/drm: dw-hdmi-qp: When enable-gpio is not configured filter hdmi 2.1 resolution

Change-Id: I4e8347480d3fcd47be75a936145ebdaee742a6a4
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>

video/drm: vop2: update pre_dither_down config

1. config vp1 pre_dither_down at split mode;
2. disable pre_dither_down at YUV 10/8 bit output and RGB 10 bit output;
3. enable pre_dither_down at RGB

video/drm: vop2: update pre_dither_down config

1. config vp1 pre_dither_down at split mode;
2. disable pre_dither_down at YUV 10/8 bit output and RGB 10 bit output;
3. enable pre_dither_down at RGB 8/6 bit output;

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: If1a39a6b0fe3c50c9cd5afebe41bb81d6d8518db

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video/drm: display: sync bus_format definitions with kernel

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ica98f112605e7dfbcf56c538a32f795e35386cb9

video/drm: display: sync func drm_mode_set_crtcinfo() with kernel

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I56ceaa5a412d815522865cafac5acc1d8becd2ba

video/drm: display: fix post csc property name

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I79b693293e3a5a922a80f7d7b789e45b0de8445c

video/drm: phy: dcphy: fix HSTX_CLK_SEL config

set HSTX_CLK_SEL 1`b1 when cphy lane rate under 500Msps,
while set HSTX_CLK_SEL 1`b1 when dphy lane rate under 1500Mbps

Change-Id: I78138efde39c08337a

video/drm: phy: dcphy: fix HSTX_CLK_SEL config

set HSTX_CLK_SEL 1`b1 when cphy lane rate under 500Msps,
while set HSTX_CLK_SEL 1`b1 when dphy lane rate under 1500Mbps

Change-Id: I78138efde39c08337ae2de0f8098c0fb9435d359
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

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video/drm: vop2: add mirror plane check for rk3566

It is needed to enable the source win before the mirror
win for rk3566.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I425a7284

video/drm: vop2: add mirror plane check for rk3566

It is needed to enable the source win before the mirror
win for rk3566.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I425a7284dc9d6c160ff6d8587eefec3bb90fa045

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video/drm: panel: add support to send spi cmds through spi device

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I9ea1b92cf44bb6f75130f251972f5793be123e9f

video/drm: vop2: add win dither_up configs

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I44b49b77ba6247e064b1133fb8f363cd0951e059

video/drm: rohm-bu18rl82: add 5ms delay after soft reset

Signed-off-by: Luo Wei <lw@rock-chips.com>
Change-Id: Ie34daf978869804644817153c5a00b2ae7f9079d

phy: rockchip-samsung-hdptx-hdmi: Fix hdmi Inter-Pair Skew exceed the limits

In hdmi2.0 resolution, the phase of D2 lane is probabilistically
ahead of other lanes. Set phy deskew FIFO works on shar

phy: rockchip-samsung-hdptx-hdmi: Fix hdmi Inter-Pair Skew exceed the limits

In hdmi2.0 resolution, the phase of D2 lane is probabilistically
ahead of other lanes. Set phy deskew FIFO works on shared pointer
to fix this problem.

According to vendor, this patch is also available for frl mode.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I62337be15a68cb3289eddb4b8b6850eb810b0f25

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