1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 #include <dm/device.h> 21 #include <dm/read.h> 22 #include <syscon.h> 23 24 #include "rockchip_display.h" 25 #include "rockchip_crtc.h" 26 #include "rockchip_connector.h" 27 #include "rockchip_vop.h" 28 29 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 30 { 31 return us * mode->clock / mode->htotal / 1000; 32 } 33 34 static inline void set_vop_mcu_rs(struct vop *vop, int v) 35 { 36 if (dm_gpio_is_valid(&vop->mcu_rs_gpio)) 37 dm_gpio_set_value(&vop->mcu_rs_gpio, v); 38 else 39 VOP_CTRL_SET(vop, mcu_rs, v); 40 } 41 42 static int to_vop_csc_mode(int csc_mode) 43 { 44 switch (csc_mode) { 45 case V4L2_COLORSPACE_SMPTE170M: 46 return CSC_BT601L; 47 case V4L2_COLORSPACE_REC709: 48 case V4L2_COLORSPACE_DEFAULT: 49 return CSC_BT709L; 50 case V4L2_COLORSPACE_JPEG: 51 return CSC_BT601F; 52 case V4L2_COLORSPACE_BT2020: 53 return CSC_BT2020; 54 default: 55 return CSC_BT709L; 56 } 57 } 58 59 static bool is_yuv_output(uint32_t bus_format) 60 { 61 switch (bus_format) { 62 case MEDIA_BUS_FMT_YUV8_1X24: 63 case MEDIA_BUS_FMT_YUV10_1X30: 64 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 65 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 66 case MEDIA_BUS_FMT_YUYV8_2X8: 67 case MEDIA_BUS_FMT_YVYU8_2X8: 68 case MEDIA_BUS_FMT_UYVY8_2X8: 69 case MEDIA_BUS_FMT_VYUY8_2X8: 70 case MEDIA_BUS_FMT_YUYV8_1X16: 71 case MEDIA_BUS_FMT_YVYU8_1X16: 72 case MEDIA_BUS_FMT_UYVY8_1X16: 73 case MEDIA_BUS_FMT_VYUY8_1X16: 74 return true; 75 default: 76 return false; 77 } 78 } 79 80 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) 81 { 82 /* 83 * FIXME: 84 * 85 * There is no media type for YUV444 output, 86 * so when out_mode is AAAA or P888, assume output is YUV444 on 87 * yuv format. 88 * 89 * From H/W testing, YUV444 mode need a rb swap. 90 */ 91 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 92 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 93 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 94 output_mode == ROCKCHIP_OUT_MODE_P888)) 95 return true; 96 else 97 return false; 98 } 99 100 static bool is_rb_swap(uint32_t bus_format, uint32_t output_mode) 101 { 102 /* 103 * The default component order of serial rgb3x8 formats 104 * is BGR. So it is needed to enable RB swap. 105 */ 106 if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 || 107 bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8) 108 return true; 109 else 110 return false; 111 } 112 113 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 114 { 115 struct crtc_state *crtc_state = &state->crtc_state; 116 struct connector_state *conn_state = &state->conn_state; 117 u32 *lut = conn_state->gamma.lut; 118 fdt_size_t lut_size; 119 int i, lut_len; 120 u32 *lut_regs; 121 122 if (!conn_state->gamma.lut) 123 return 0; 124 125 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut"); 126 if (i < 0) { 127 printf("Warning: vop not support gamma\n"); 128 return 0; 129 } 130 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size); 131 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 132 printf("failed to get gamma lut register\n"); 133 return 0; 134 } 135 lut_len = lut_size / 4; 136 if (lut_len != 256 && lut_len != 1024) { 137 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 138 return 0; 139 } 140 141 if (conn_state->gamma.size != lut_len) { 142 int size = conn_state->gamma.size; 143 u32 j, r, g, b, color; 144 145 for (i = 0; i < lut_len; i++) { 146 j = i * size / lut_len; 147 r = lut[j] / size / size * lut_len / size; 148 g = lut[j] / size % size * lut_len / size; 149 b = lut[j] % size * lut_len / size; 150 color = r * lut_len * lut_len + g * lut_len + b; 151 152 writel(color, lut_regs + (i << 2)); 153 } 154 } else { 155 for (i = 0; i < lut_len; i++) 156 writel(lut[i], lut_regs + (i << 2)); 157 } 158 159 VOP_CTRL_SET(vop, dsp_lut_en, 1); 160 VOP_CTRL_SET(vop, update_gamma_lut, 1); 161 162 return 0; 163 } 164 165 static void vop_post_config(struct display_state *state, struct vop *vop) 166 { 167 struct connector_state *conn_state = &state->conn_state; 168 struct drm_display_mode *mode = &conn_state->mode; 169 u16 vtotal = mode->crtc_vtotal; 170 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 171 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 172 u16 hdisplay = mode->crtc_hdisplay; 173 u16 vdisplay = mode->crtc_vdisplay; 174 u16 hsize = hdisplay * (conn_state->overscan.left_margin + conn_state->overscan.right_margin) / 200; 175 u16 vsize = vdisplay * (conn_state->overscan.top_margin + conn_state->overscan.bottom_margin) / 200; 176 u16 hact_end, vact_end; 177 u32 val; 178 179 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 180 vsize = round_down(vsize, 2); 181 182 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 183 hact_end = hact_st + hsize; 184 val = hact_st << 16; 185 val |= hact_end; 186 187 VOP_CTRL_SET(vop, hpost_st_end, val); 188 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 189 vact_end = vact_st + vsize; 190 val = vact_st << 16; 191 val |= vact_end; 192 VOP_CTRL_SET(vop, vpost_st_end, val); 193 val = scl_cal_scale2(vdisplay, vsize) << 16; 194 val |= scl_cal_scale2(hdisplay, hsize); 195 VOP_CTRL_SET(vop, post_scl_factor, val); 196 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 197 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 198 VOP_CTRL_SET(vop, post_scl_ctrl, 199 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 200 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 201 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 202 u16 vact_st_f1 = vtotal + vact_st + 1; 203 u16 vact_end_f1 = vact_st_f1 + vsize; 204 205 val = vact_st_f1 << 16 | vact_end_f1; 206 VOP_CTRL_SET(vop, vpost_st_end_f1, val); 207 } 208 } 209 210 static void vop_mcu_mode(struct display_state *state, struct vop *vop) 211 { 212 struct crtc_state *crtc_state = &state->crtc_state; 213 214 VOP_CTRL_SET(vop, mcu_clk_sel, 1); 215 VOP_CTRL_SET(vop, mcu_type, 1); 216 217 VOP_CTRL_SET(vop, mcu_hold_mode, 1); 218 VOP_CTRL_SET(vop, mcu_pix_total, crtc_state->mcu_timing.mcu_pix_total); 219 VOP_CTRL_SET(vop, mcu_cs_pst, crtc_state->mcu_timing.mcu_cs_pst); 220 VOP_CTRL_SET(vop, mcu_cs_pend, crtc_state->mcu_timing.mcu_cs_pend); 221 VOP_CTRL_SET(vop, mcu_rw_pst, crtc_state->mcu_timing.mcu_rw_pst); 222 VOP_CTRL_SET(vop, mcu_rw_pend, crtc_state->mcu_timing.mcu_rw_pend); 223 } 224 225 static int rockchip_vop_preinit(struct display_state *state) 226 { 227 const struct vop_data *vop_data = state->crtc_state.crtc->data; 228 229 state->crtc_state.max_output = vop_data->max_output; 230 231 return 0; 232 } 233 234 static int rockchip_vop_init(struct display_state *state) 235 { 236 struct crtc_state *crtc_state = &state->crtc_state; 237 struct connector_state *conn_state = &state->conn_state; 238 struct drm_display_mode *mode = &conn_state->mode; 239 const struct rockchip_crtc *crtc = crtc_state->crtc; 240 const struct vop_data *vop_data = crtc->data; 241 struct vop *vop; 242 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 243 u16 hdisplay = mode->crtc_hdisplay; 244 u16 htotal = mode->crtc_htotal; 245 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 246 u16 hact_end = hact_st + hdisplay; 247 u16 vdisplay = mode->crtc_vdisplay; 248 u16 vtotal = mode->crtc_vtotal; 249 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 250 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 251 u16 vact_end = vact_st + vdisplay; 252 struct clk dclk; 253 u32 val, act_end; 254 int ret; 255 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 256 u16 post_csc_mode; 257 bool dclk_inv; 258 259 vop = malloc(sizeof(*vop)); 260 if (!vop) 261 return -ENOMEM; 262 memset(vop, 0, sizeof(*vop)); 263 264 crtc_state->private = vop; 265 vop->regs = dev_read_addr_ptr(crtc_state->dev); 266 vop->regsbak = malloc(vop_data->reg_len); 267 vop->win = vop_data->win; 268 vop->win_offset = vop_data->win_offset; 269 vop->ctrl = vop_data->ctrl; 270 vop->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 271 if (vop->grf <= 0) 272 printf("%s: Get syscon grf failed (ret=%p)\n", 273 __func__, vop->grf); 274 275 vop->grf_ctrl = vop_data->grf_ctrl; 276 vop->line_flag = vop_data->line_flag; 277 vop->csc_table = vop_data->csc_table; 278 vop->win_csc = vop_data->win_csc; 279 vop->version = vop_data->version; 280 281 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 282 ret = clk_set_defaults(crtc_state->dev); 283 if (ret) 284 debug("%s clk_set_defaults failed %d\n", __func__, ret); 285 286 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 287 if (!ret) 288 ret = clk_set_rate(&dclk, mode->crtc_clock * 1000); 289 if (IS_ERR_VALUE(ret)) { 290 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 291 return ret; 292 } 293 294 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 295 296 rockchip_vop_init_gamma(vop, state); 297 298 ret = gpio_request_by_name(crtc_state->dev, "mcu-rs-gpios", 299 0, &vop->mcu_rs_gpio, GPIOD_IS_OUT); 300 if (ret && ret != -ENOENT) 301 printf("%s: Cannot get mcu rs GPIO: %d\n", __func__, ret); 302 303 VOP_CTRL_SET(vop, global_regdone_en, 1); 304 VOP_CTRL_SET(vop, axi_outstanding_max_num, 30); 305 VOP_CTRL_SET(vop, axi_max_outstanding_en, 1); 306 VOP_CTRL_SET(vop, reg_done_frm, 1); 307 VOP_CTRL_SET(vop, win_gate[0], 1); 308 VOP_CTRL_SET(vop, win_gate[1], 1); 309 VOP_CTRL_SET(vop, win_channel[0], 0x12); 310 VOP_CTRL_SET(vop, win_channel[1], 0x34); 311 VOP_CTRL_SET(vop, win_channel[2], 0x56); 312 VOP_CTRL_SET(vop, dsp_blank, 0); 313 314 dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0; 315 /* For improving signal quality, dclk need to be inverted by default on rv1106. */ 316 if ((VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) == 12)) 317 dclk_inv = !dclk_inv; 318 VOP_CTRL_SET(vop, dclk_pol, dclk_inv); 319 320 val = 0x8; 321 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 322 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 323 VOP_CTRL_SET(vop, pin_pol, val); 324 325 switch (conn_state->type) { 326 case DRM_MODE_CONNECTOR_LVDS: 327 VOP_CTRL_SET(vop, rgb_en, 1); 328 VOP_CTRL_SET(vop, rgb_pin_pol, val); 329 VOP_CTRL_SET(vop, rgb_dclk_pol, dclk_inv); 330 VOP_CTRL_SET(vop, lvds_en, 1); 331 VOP_CTRL_SET(vop, lvds_pin_pol, val); 332 VOP_CTRL_SET(vop, lvds_dclk_pol, dclk_inv); 333 if (!IS_ERR_OR_NULL(vop->grf)) 334 VOP_GRF_SET(vop, grf_dclk_inv, dclk_inv); 335 break; 336 case DRM_MODE_CONNECTOR_eDP: 337 VOP_CTRL_SET(vop, edp_en, 1); 338 VOP_CTRL_SET(vop, edp_pin_pol, val); 339 VOP_CTRL_SET(vop, edp_dclk_pol, dclk_inv); 340 break; 341 case DRM_MODE_CONNECTOR_HDMIA: 342 VOP_CTRL_SET(vop, hdmi_en, 1); 343 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 344 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1); 345 break; 346 case DRM_MODE_CONNECTOR_DSI: 347 VOP_CTRL_SET(vop, mipi_en, 1); 348 VOP_CTRL_SET(vop, mipi_pin_pol, val); 349 VOP_CTRL_SET(vop, mipi_dclk_pol, dclk_inv); 350 VOP_CTRL_SET(vop, mipi_dual_channel_en, 351 !!(conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)); 352 VOP_CTRL_SET(vop, data01_swap, 353 !!(conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) || 354 crtc_state->dual_channel_swap); 355 break; 356 case DRM_MODE_CONNECTOR_DisplayPort: 357 VOP_CTRL_SET(vop, dp_dclk_pol, 0); 358 VOP_CTRL_SET(vop, dp_pin_pol, val); 359 VOP_CTRL_SET(vop, dp_en, 1); 360 break; 361 case DRM_MODE_CONNECTOR_TV: 362 if (vdisplay == CVBS_PAL_VDISPLAY) 363 VOP_CTRL_SET(vop, tve_sw_mode, 1); 364 else 365 VOP_CTRL_SET(vop, tve_sw_mode, 0); 366 VOP_CTRL_SET(vop, tve_dclk_pol, 1); 367 VOP_CTRL_SET(vop, tve_dclk_en, 1); 368 /* use the same pol reg with hdmi */ 369 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 370 VOP_CTRL_SET(vop, sw_genlock, 1); 371 VOP_CTRL_SET(vop, sw_uv_offset_en, 1); 372 VOP_CTRL_SET(vop, dither_up, 1); 373 break; 374 default: 375 printf("unsupport connector_type[%d]\n", conn_state->type); 376 } 377 378 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 379 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 380 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 381 382 switch (conn_state->bus_format) { 383 case MEDIA_BUS_FMT_RGB565_1X16: 384 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 385 break; 386 case MEDIA_BUS_FMT_RGB666_1X18: 387 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 388 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 389 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 390 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 391 break; 392 case MEDIA_BUS_FMT_YUV8_1X24: 393 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 394 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1); 395 break; 396 case MEDIA_BUS_FMT_YUV10_1X30: 397 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 398 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 399 break; 400 case MEDIA_BUS_FMT_RGB888_1X24: 401 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 402 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 403 default: 404 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 405 break; 406 } 407 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 408 val |= PRE_DITHER_DOWN_EN(0); 409 else 410 val |= PRE_DITHER_DOWN_EN(1); 411 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 412 VOP_CTRL_SET(vop, dither_down, val); 413 414 VOP_CTRL_SET(vop, dclk_ddr, 415 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 416 VOP_CTRL_SET(vop, hdmi_dclk_out_en, 417 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 418 419 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode) || 420 is_rb_swap(conn_state->bus_format, conn_state->output_mode)) 421 VOP_CTRL_SET(vop, dsp_rb_swap, 1); 422 else 423 VOP_CTRL_SET(vop, dsp_data_swap, 0); 424 425 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 426 427 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) { 428 yuv_overlay = is_yuv_output(conn_state->bus_format); 429 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay); 430 } 431 /* 432 * todo: r2y for win csc 433 */ 434 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format)); 435 436 if (yuv_overlay) { 437 if (!is_yuv_output(conn_state->bus_format)) 438 post_y2r_en = true; 439 } else { 440 if (is_yuv_output(conn_state->bus_format)) 441 post_r2y_en = true; 442 } 443 444 crtc_state->yuv_overlay = yuv_overlay; 445 post_csc_mode = to_vop_csc_mode(conn_state->color_space); 446 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en); 447 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en); 448 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode); 449 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode); 450 451 /* 452 * Background color is 10bit depth if vop version >= 3.5 453 */ 454 if (!is_yuv_output(conn_state->bus_format)) 455 val = 0; 456 else if (VOP_MAJOR(vop->version) == 3 && 457 VOP_MINOR(vop->version) >= 5) 458 val = 0x20010200; 459 else 460 val = 0x801080; 461 VOP_CTRL_SET(vop, dsp_background, val); 462 463 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 464 val = hact_st << 16; 465 val |= hact_end; 466 VOP_CTRL_SET(vop, hact_st_end, val); 467 val = vact_st << 16; 468 val |= vact_end; 469 VOP_CTRL_SET(vop, vact_st_end, val); 470 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 471 u16 vact_st_f1 = vtotal + vact_st + 1; 472 u16 vact_end_f1 = vact_st_f1 + vdisplay; 473 474 val = vact_st_f1 << 16 | vact_end_f1; 475 VOP_CTRL_SET(vop, vact_st_end_f1, val); 476 477 val = vtotal << 16 | (vtotal + vsync_len); 478 VOP_CTRL_SET(vop, vs_st_end_f1, val); 479 VOP_CTRL_SET(vop, dsp_interlace, 1); 480 VOP_CTRL_SET(vop, p2i_en, 1); 481 vtotal += vtotal + 1; 482 act_end = vact_end_f1; 483 } else { 484 VOP_CTRL_SET(vop, dsp_interlace, 0); 485 VOP_CTRL_SET(vop, p2i_en, 0); 486 act_end = vact_end; 487 } 488 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 489 vop_post_config(state, vop); 490 VOP_CTRL_SET(vop, core_dclk_div, 491 !!(mode->flags & DRM_MODE_FLAG_DBLCLK)); 492 493 VOP_LINE_FLAG_SET(vop, line_flag_num[0], act_end - 3); 494 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 495 act_end - us_to_vertical_line(mode, 1000)); 496 if (state->crtc_state.mcu_timing.mcu_pix_total > 0) 497 vop_mcu_mode(state, vop); 498 vop_cfg_done(vop); 499 500 return 0; 501 } 502 503 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 504 uint32_t dst, bool is_horizontal, 505 int vsu_mode, int *vskiplines) 506 { 507 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 508 509 if (is_horizontal) { 510 if (mode == SCALE_UP) 511 val = GET_SCL_FT_BIC(src, dst); 512 else if (mode == SCALE_DOWN) 513 val = GET_SCL_FT_BILI_DN(src, dst); 514 } else { 515 if (mode == SCALE_UP) { 516 if (vsu_mode == SCALE_UP_BIL) 517 val = GET_SCL_FT_BILI_UP(src, dst); 518 else 519 val = GET_SCL_FT_BIC(src, dst); 520 } else if (mode == SCALE_DOWN) { 521 if (vskiplines) { 522 *vskiplines = scl_get_vskiplines(src, dst); 523 val = scl_get_bili_dn_vskip(src, dst, 524 *vskiplines); 525 } else { 526 val = GET_SCL_FT_BILI_DN(src, dst); 527 } 528 } 529 } 530 531 return val; 532 } 533 534 static void scl_vop_cal_scl_fac(struct vop *vop, 535 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 536 uint32_t dst_h, uint32_t pixel_format) 537 { 538 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 539 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 540 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 541 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 542 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 543 bool is_yuv = false; 544 uint16_t cbcr_src_w = src_w / hsub; 545 uint16_t cbcr_src_h = src_h / vsub; 546 uint16_t vsu_mode; 547 uint16_t lb_mode; 548 uint32_t val; 549 int vskiplines = 0; 550 551 if (!vop->win->scl) 552 return; 553 554 if (!vop->win->scl->ext) { 555 VOP_SCL_SET(vop, scale_yrgb_x, 556 scl_cal_scale2(src_w, dst_w)); 557 VOP_SCL_SET(vop, scale_yrgb_y, 558 scl_cal_scale2(src_h, dst_h)); 559 if (is_yuv) { 560 VOP_SCL_SET(vop, scale_cbcr_x, 561 scl_cal_scale2(src_w, dst_w)); 562 VOP_SCL_SET(vop, scale_cbcr_y, 563 scl_cal_scale2(src_h, dst_h)); 564 } 565 return; 566 } 567 568 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 569 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 570 571 if (is_yuv) { 572 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 573 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 574 if (cbcr_hor_scl_mode == SCALE_DOWN) 575 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 576 else 577 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 578 } else { 579 if (yrgb_hor_scl_mode == SCALE_DOWN) 580 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 581 else 582 lb_mode = scl_vop_cal_lb_mode(src_w, false); 583 } 584 585 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 586 if (lb_mode == LB_RGB_3840X2) { 587 if (yrgb_ver_scl_mode != SCALE_NONE) { 588 printf("ERROR : not allow yrgb ver scale\n"); 589 return; 590 } 591 if (cbcr_ver_scl_mode != SCALE_NONE) { 592 printf("ERROR : not allow cbcr ver scale\n"); 593 return; 594 } 595 vsu_mode = SCALE_UP_BIL; 596 } else if (lb_mode == LB_RGB_2560X4) { 597 vsu_mode = SCALE_UP_BIL; 598 } else { 599 vsu_mode = SCALE_UP_BIC; 600 } 601 602 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 603 true, 0, NULL); 604 VOP_SCL_SET(vop, scale_yrgb_x, val); 605 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 606 false, vsu_mode, &vskiplines); 607 VOP_SCL_SET(vop, scale_yrgb_y, val); 608 609 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 610 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 611 612 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 613 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 614 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 615 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 616 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 617 if (is_yuv) { 618 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 619 dst_w, true, 0, NULL); 620 VOP_SCL_SET(vop, scale_cbcr_x, val); 621 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 622 dst_h, false, vsu_mode, &vskiplines); 623 VOP_SCL_SET(vop, scale_cbcr_y, val); 624 625 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 626 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 627 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 628 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 629 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 630 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 631 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 632 } 633 } 634 635 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table) 636 { 637 int i; 638 639 /* 640 * so far the csc offset is not 0 and in the feature the csc offset 641 * impossible be 0, so when the offset is 0, should return here. 642 */ 643 if (!table || offset == 0) 644 return; 645 646 for (i = 0; i < 8; i++) 647 vop_writel(vop, offset + i * 4, table[i]); 648 } 649 650 static int rockchip_vop_setup_csc_table(struct display_state *state) 651 { 652 struct crtc_state *crtc_state = &state->crtc_state; 653 struct connector_state *conn_state = &state->conn_state; 654 struct vop *vop = crtc_state->private; 655 const uint32_t *csc_table = NULL; 656 657 if (!vop->csc_table || !crtc_state->yuv_overlay) 658 return 0; 659 /* todo: only implement r2y*/ 660 switch (conn_state->color_space) { 661 case V4L2_COLORSPACE_SMPTE170M: 662 csc_table = vop->csc_table->r2y_bt601_12_235; 663 break; 664 case V4L2_COLORSPACE_REC709: 665 case V4L2_COLORSPACE_DEFAULT: 666 case V4L2_COLORSPACE_JPEG: 667 csc_table = vop->csc_table->r2y_bt709; 668 break; 669 case V4L2_COLORSPACE_BT2020: 670 csc_table = vop->csc_table->r2y_bt2020; 671 break; 672 default: 673 csc_table = vop->csc_table->r2y_bt601; 674 break; 675 } 676 677 vop_load_csc_table(vop, vop->win_csc->r2y_offset, csc_table); 678 VOP_WIN_CSC_SET(vop, r2y_en, 1); 679 680 return 0; 681 } 682 683 static int rockchip_vop_set_plane(struct display_state *state) 684 { 685 struct crtc_state *crtc_state = &state->crtc_state; 686 const struct rockchip_crtc *crtc = crtc_state->crtc; 687 const struct vop_data *vop_data = crtc->data; 688 struct connector_state *conn_state = &state->conn_state; 689 struct drm_display_mode *mode = &conn_state->mode; 690 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 691 struct vop *vop = crtc_state->private; 692 int src_w = crtc_state->src_rect.w; 693 int src_h = crtc_state->src_rect.h; 694 int crtc_x = crtc_state->crtc_rect.x; 695 int crtc_y = crtc_state->crtc_rect.y; 696 int crtc_w = crtc_state->crtc_rect.w; 697 int crtc_h = crtc_state->crtc_rect.h; 698 int xvir = crtc_state->xvir; 699 int x_mirror = 0, y_mirror = 0; 700 701 if (crtc_w > crtc_state->max_output.width) { 702 printf("ERROR: output w[%d] exceeded max width[%d]\n", 703 crtc_w, crtc_state->max_output.width); 704 return -EINVAL; 705 } 706 707 act_info = (src_h - 1) << 16; 708 act_info |= (src_w - 1) & 0xffff; 709 710 dsp_info = (crtc_h - 1) << 16; 711 dsp_info |= (crtc_w - 1) & 0xffff; 712 713 dsp_stx = crtc_x + mode->crtc_htotal - mode->crtc_hsync_start; 714 dsp_sty = crtc_y + mode->crtc_vtotal - mode->crtc_vsync_start; 715 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 716 /* 717 * vop full need to treats rgb888 as bgr888 so we reverse the rb swap to workaround 718 */ 719 if (crtc_state->format == ROCKCHIP_FMT_RGB888 && VOP_MAJOR(vop_data->version) == 3) 720 crtc_state->rb_swap = !crtc_state->rb_swap; 721 722 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 723 y_mirror = 1; 724 else 725 y_mirror = 0; 726 if (mode->flags & DRM_MODE_FLAG_XMIRROR) 727 x_mirror = 1; 728 else 729 x_mirror = 0; 730 if (crtc_state->ymirror ^ y_mirror) 731 y_mirror = 1; 732 else 733 y_mirror = 0; 734 if (y_mirror) { 735 if (VOP_CTRL_SUPPORT(vop, ymirror)) 736 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 737 else 738 y_mirror = 0; 739 } 740 VOP_CTRL_SET(vop, ymirror, y_mirror); 741 VOP_CTRL_SET(vop, xmirror, x_mirror); 742 743 VOP_WIN_SET(vop, format, crtc_state->format); 744 VOP_WIN_SET(vop, yrgb_vir, xvir); 745 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 746 747 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 748 crtc_state->format); 749 750 VOP_WIN_SET(vop, act_info, act_info); 751 VOP_WIN_SET(vop, dsp_info, dsp_info); 752 VOP_WIN_SET(vop, dsp_st, dsp_st); 753 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 754 755 VOP_WIN_SET(vop, src_alpha_ctl, 0); 756 757 rockchip_vop_setup_csc_table(state); 758 VOP_WIN_SET(vop, enable, 1); 759 VOP_WIN_SET(vop, gate, 1); 760 vop_cfg_done(vop); 761 762 return 0; 763 } 764 765 static int rockchip_vop_prepare(struct display_state *state) 766 { 767 return 0; 768 } 769 770 static int rockchip_vop_enable(struct display_state *state) 771 { 772 struct crtc_state *crtc_state = &state->crtc_state; 773 struct vop *vop = crtc_state->private; 774 775 VOP_CTRL_SET(vop, standby, 0); 776 vop_cfg_done(vop); 777 if (crtc_state->mcu_timing.mcu_pix_total > 0) 778 VOP_CTRL_SET(vop, mcu_hold_mode, 0); 779 780 return 0; 781 } 782 783 static int rockchip_vop_disable(struct display_state *state) 784 { 785 struct crtc_state *crtc_state = &state->crtc_state; 786 struct vop *vop = crtc_state->private; 787 788 VOP_CTRL_SET(vop, standby, 1); 789 vop_cfg_done(vop); 790 return 0; 791 } 792 793 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 794 { 795 #if 0 796 struct crtc_state *crtc_state = &state->crtc_state; 797 struct panel_state *pstate = &state->panel_state; 798 uint32_t phandle; 799 char path[100]; 800 int ret, dsp_lut_node; 801 802 if (!ofnode_valid(pstate->dsp_lut_node)) 803 return 0; 804 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 805 if (ret < 0) { 806 printf("failed to get dsp_lut path[%s], ret=%d\n", 807 path, ret); 808 return ret; 809 } 810 811 dsp_lut_node = fdt_path_offset(blob, path); 812 phandle = fdt_get_phandle(blob, dsp_lut_node); 813 if (!phandle) { 814 phandle = fdt_alloc_phandle(blob); 815 if (!phandle) { 816 printf("failed to alloc phandle\n"); 817 return -ENOMEM; 818 } 819 820 fdt_set_phandle(blob, dsp_lut_node, phandle); 821 } 822 823 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 824 if (ret < 0) { 825 printf("failed to get route path[%s], ret=%d\n", 826 path, ret); 827 return ret; 828 } 829 830 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 831 #endif 832 return 0; 833 } 834 835 static int rockchip_vop_send_mcu_cmd(struct display_state *state, 836 u32 type, u32 value) 837 { 838 struct crtc_state *crtc_state = &state->crtc_state; 839 struct vop *vop = crtc_state->private; 840 841 if (vop) { 842 switch (type) { 843 case MCU_WRCMD: 844 set_vop_mcu_rs(vop, 0); 845 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 846 set_vop_mcu_rs(vop, 1); 847 break; 848 case MCU_WRDATA: 849 set_vop_mcu_rs(vop, 1); 850 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 851 break; 852 case MCU_SETBYPASS: 853 VOP_CTRL_SET(vop, mcu_bypass, value ? 1 : 0); 854 break; 855 default: 856 break; 857 } 858 } 859 860 return 0; 861 } 862 863 static int rockchip_vop_mode_valid(struct display_state *state) 864 { 865 struct connector_state *conn_state = &state->conn_state; 866 struct drm_display_mode *mode = &conn_state->mode; 867 struct videomode vm; 868 869 drm_display_mode_to_videomode(mode, &vm); 870 871 if (vm.hactive < 32 || vm.vactive < 32 || 872 (vm.hfront_porch * vm.hsync_len * vm.hback_porch * 873 vm.vfront_porch * vm.vsync_len * vm.vback_porch == 0)) { 874 printf("ERROR: unsupported display timing\n"); 875 return -EINVAL; 876 } 877 878 return 0; 879 } 880 881 static int rockchip_vop_plane_check(struct display_state *state) 882 { 883 struct crtc_state *crtc_state = &state->crtc_state; 884 const struct rockchip_crtc *crtc = crtc_state->crtc; 885 const struct vop_data *vop_data = crtc->data; 886 const struct vop_win *win = vop_data->win; 887 struct display_rect *src = &crtc_state->src_rect; 888 struct display_rect *dst = &crtc_state->crtc_rect; 889 int min_scale, max_scale; 890 int hscale, vscale; 891 892 min_scale = win->scl ? FRAC_16_16(1, 8) : VOP_PLANE_NO_SCALING; 893 max_scale = win->scl ? FRAC_16_16(8, 1) : VOP_PLANE_NO_SCALING; 894 895 hscale = display_rect_calc_hscale(src, dst, min_scale, max_scale); 896 vscale = display_rect_calc_vscale(src, dst, min_scale, max_scale); 897 if (hscale < 0 || vscale < 0) { 898 printf("ERROR: scale factor is out of range\n"); 899 return -ERANGE; 900 } 901 902 return 0; 903 } 904 905 static int rockchip_vop_mode_fixup(struct display_state *state) 906 { 907 struct crtc_state *crtc_state = &state->crtc_state; 908 struct connector_state *conn_state = &state->conn_state; 909 struct drm_display_mode *mode = &conn_state->mode; 910 911 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE); 912 913 mode->crtc_clock *= rockchip_drm_get_cycles_per_pixel(conn_state->bus_format); 914 if (crtc_state->mcu_timing.mcu_pix_total) 915 mode->crtc_clock *= crtc_state->mcu_timing.mcu_pix_total + 1; 916 917 return 0; 918 } 919 920 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 921 .preinit = rockchip_vop_preinit, 922 .init = rockchip_vop_init, 923 .set_plane = rockchip_vop_set_plane, 924 .prepare = rockchip_vop_prepare, 925 .enable = rockchip_vop_enable, 926 .disable = rockchip_vop_disable, 927 .fixup_dts = rockchip_vop_fixup_dts, 928 .send_mcu_cmd = rockchip_vop_send_mcu_cmd, 929 .mode_valid = rockchip_vop_mode_valid, 930 .plane_check = rockchip_vop_plane_check, 931 .mode_fixup = rockchip_vop_mode_fixup, 932 }; 933