| 428eb1cf | 11-Sep-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
UPSTREAM: rockchip: timer: Convert to livetree
Update the Rockchip timer driver to support a live device tree.
Change-Id: Ia7d704245e17907954428bd2bc1c5d895114797f
Signed-off-by: Philipp Tomsich <p
UPSTREAM: rockchip: timer: Convert to livetree
Update the Rockchip timer driver to support a live device tree.
Change-Id: Ia7d704245e17907954428bd2bc1c5d895114797f
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 6675c952f20b7b3cfedd57c9c49305289a89403c)
show more ...
|
| fdb35717 | 11-Sep-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
UPSTREAM: rockchip: timer: implement timer_get_boot_us
To make the Rockchip DM timer driver useful for the timing of
bootstages, we need a few enhancements:
- This implements timer_get_boot_us.
-
UPSTREAM: rockchip: timer: implement timer_get_boot_us
To make the Rockchip DM timer driver useful for the timing of
bootstages, we need a few enhancements:
- This implements timer_get_boot_us.
- This avoids reinitialising the timer, if it has already been
set up (e.g. by our TPL and SPL stages). Now, we have a single
timebase ticking from TPL through the full U-Boot.
- This adds support for reading the timer even before the
device-model is ready: we find the timer via /chosen/tick-timer,
then read its address and clock-frequency, and finally read the
timeval directly).
Change-Id: I5f7d06f77c143482b28db7471600fdc5f39b824c
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit cc7ce94e02799c5caa6d9c89350152f00ba3eb90)
show more ...
|
| 5867875c | 11-Sep-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
UPSTREAM: dm: timer: handle being called before dm_root is ready
When used with bootstage recording, dm_timer_init may be called
surprisingly early: i.e. before dm_root is ready. To deal with
this c
UPSTREAM: dm: timer: handle being called before dm_root is ready
When used with bootstage recording, dm_timer_init may be called
surprisingly early: i.e. before dm_root is ready. To deal with
this case, we explicitly check for this condition and return
-EAGAIN to the caller (refer to drivers/timer/rockchip_timer.c
for a case where this is needed/used).
Change-Id: Ia35fea65924a73b6cc4b182ba28823b207be8e6f
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit af823151641b1a9a8eae8c3b111f5fa27e6873ac)
show more ...
|
| 1168d2dd | 28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar)
This adds a device-model driver for the timer block in the RK3368 (and
similar devices that share the same timer block, such a
rockchip: timer: add device-model timer driver for RK3368 (and similar)
This adds a device-model driver for the timer block in the RK3368 (and
similar devices that share the same timer block, such as the RK3288) for
the down-counting (i.e. non-secure) timers.
This allows us to configure U-Boot for the RK3368 in such a way that
we can run with the secure timer inaccessible or uninitialised (note
that the ARMv8 generic timer does not count, if the secure timer is
not enabled).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
| e9e5d9d2 | 28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support
To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing
dm: timer: normalise SPL and TPL support
To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing
decision for each stage and under control of $(SPL_TPL_)TIMER
instead of having the two-level configuration with TIMER and
$(SPL_TPL_)TIMER_SUPPORT
- when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can
not be compiled in
This normalises configuration to $(SPL_TPL_)TIMER and moves the config
options to drivers/timer/Kconfig (and cleans up the collateral damage
to some defconfigs that had SPL_TIMER_SUPPORT enabled).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 167a4016 | 26-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr()
Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr(), as that
better describes what the routine does.
This keeps in sync with Linux ke
x86: tsc: Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr()
Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr(), as that
better describes what the routine does.
This keeps in sync with Linux kernel commit:
02c0cd2: x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
| f5757154 | 26-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Correct Silvermont reference clock values
Atom processors use a 19.2 MHz crystal oscillator.
Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz.
Later processors generat
x86: tsc: Correct Silvermont reference clock values
Atom processors use a 19.2 MHz crystal oscillator.
Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz.
Later processors generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz.
Update the Silvermont-based tables accordingly, matching the Software
Developers Manual.
Also, correct a 166 MHz entry that should have been 116 MHz, and add
a missing 80 MHz entry for VLV2.
This keeps in sync with Linux kernel commit:
05680e7: x86/tsc_msr: Correct Silvermont reference clock values
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
| c6367748 | 26-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Update comments and expand definitions in freq_desc_tables[]
Some processor abbreviations in the comments of freq_desc_tables[]
are obscure. This updates part of these to mention processor
x86: tsc: Update comments and expand definitions in freq_desc_tables[]
Some processor abbreviations in the comments of freq_desc_tables[]
are obscure. This updates part of these to mention processors
that are known to us. Also expand frequency definitions.
This keeps in sync with Linux kernel commit:
9e0cae9: x86/tsc_msr: Update comments, expand definitions
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
| fde1801e | 26-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Remove the fail handling in try_msr_calibrate_tsc()
If either ratio or freq is zero, the return value is zero. There
is no need to create a fail branch and return zero there.
This keeps i
x86: tsc: Remove the fail handling in try_msr_calibrate_tsc()
If either ratio or freq is zero, the return value is zero. There
is no need to create a fail branch and return zero there.
This keeps in sync with Linux kernel commit:
14bb4e3: x86/tsc_msr: Remove debugging messages
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 0b992e49 | 26-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Identify Intel-specific code
try_msr_calibrate_tsc() is currently Intel-specific, and should not
execute on any other vendor's parts.
This keeps in sync with Linux kernel commit:
ba8268
x86: tsc: Identify Intel-specific code
try_msr_calibrate_tsc() is currently Intel-specific, and should not
execute on any other vendor's parts.
This keeps in sync with Linux kernel commit:
ba82683: x86/tsc_msr: Identify Intel-specific code
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|