1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * TSC calibration codes are adapted from Linux kernel 5 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <malloc.h> 13 #include <timer.h> 14 #include <asm/cpu.h> 15 #include <asm/io.h> 16 #include <asm/i8254.h> 17 #include <asm/ibmpc.h> 18 #include <asm/msr.h> 19 #include <asm/u-boot-x86.h> 20 21 /* CPU reference clock frequency: in KHz */ 22 #define FREQ_83 83200 23 #define FREQ_100 99840 24 #define FREQ_133 133200 25 #define FREQ_166 166400 26 27 #define MAX_NUM_FREQS 8 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 /* 32 * According to Intel 64 and IA-32 System Programming Guide, 33 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be 34 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40]. 35 * Unfortunately some Intel Atom SoCs aren't quite compliant to this, 36 * so we need manually differentiate SoC families. This is what the 37 * field msr_plat does. 38 */ 39 struct freq_desc { 40 u8 x86_family; /* CPU family */ 41 u8 x86_model; /* model */ 42 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */ 43 u8 msr_plat; 44 u32 freqs[MAX_NUM_FREQS]; 45 }; 46 47 static struct freq_desc freq_desc_tables[] = { 48 /* PNW */ 49 { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } }, 50 /* CLV+ */ 51 { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } }, 52 /* TNG */ 53 { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } }, 54 /* VLV2 */ 55 { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } }, 56 /* Ivybridge */ 57 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } }, 58 /* ANN */ 59 { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } }, 60 }; 61 62 static int match_cpu(u8 family, u8 model) 63 { 64 int i; 65 66 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) { 67 if ((family == freq_desc_tables[i].x86_family) && 68 (model == freq_desc_tables[i].x86_model)) 69 return i; 70 } 71 72 return -1; 73 } 74 75 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */ 76 #define id_to_freq(cpu_index, freq_id) \ 77 (freq_desc_tables[cpu_index].freqs[freq_id]) 78 79 /* 80 * Do MSR calibration only for known/supported CPUs. 81 * 82 * Returns the calibration value or 0 if MSR calibration failed. 83 */ 84 static unsigned long __maybe_unused try_msr_calibrate_tsc(void) 85 { 86 u32 lo, hi, ratio, freq_id, freq; 87 unsigned long res; 88 int cpu_index; 89 90 if (gd->arch.x86_vendor != X86_VENDOR_INTEL) 91 return 0; 92 93 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model); 94 if (cpu_index < 0) 95 return 0; 96 97 if (freq_desc_tables[cpu_index].msr_plat) { 98 rdmsr(MSR_PLATFORM_INFO, lo, hi); 99 ratio = (lo >> 8) & 0xff; 100 } else { 101 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); 102 ratio = (hi >> 8) & 0x1f; 103 } 104 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio); 105 106 if (freq_desc_tables[cpu_index].msr_plat == 2) { 107 /* TODO: Figure out how best to deal with this */ 108 freq = FREQ_100; 109 debug("Using frequency: %u KHz\n", freq); 110 } else { 111 /* Get FSB FREQ ID */ 112 rdmsr(MSR_FSB_FREQ, lo, hi); 113 freq_id = lo & 0x7; 114 freq = id_to_freq(cpu_index, freq_id); 115 debug("Resolved frequency ID: %u, frequency: %u KHz\n", 116 freq_id, freq); 117 } 118 119 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ 120 res = freq * ratio / 1000; 121 debug("TSC runs at %lu MHz\n", res); 122 123 return res; 124 } 125 126 /* 127 * This reads the current MSB of the PIT counter, and 128 * checks if we are running on sufficiently fast and 129 * non-virtualized hardware. 130 * 131 * Our expectations are: 132 * 133 * - the PIT is running at roughly 1.19MHz 134 * 135 * - each IO is going to take about 1us on real hardware, 136 * but we allow it to be much faster (by a factor of 10) or 137 * _slightly_ slower (ie we allow up to a 2us read+counter 138 * update - anything else implies a unacceptably slow CPU 139 * or PIT for the fast calibration to work. 140 * 141 * - with 256 PIT ticks to read the value, we have 214us to 142 * see the same MSB (and overhead like doing a single TSC 143 * read per MSB value etc). 144 * 145 * - We're doing 2 reads per loop (LSB, MSB), and we expect 146 * them each to take about a microsecond on real hardware. 147 * So we expect a count value of around 100. But we'll be 148 * generous, and accept anything over 50. 149 * 150 * - if the PIT is stuck, and we see *many* more reads, we 151 * return early (and the next caller of pit_expect_msb() 152 * then consider it a failure when they don't see the 153 * next expected value). 154 * 155 * These expectations mean that we know that we have seen the 156 * transition from one expected value to another with a fairly 157 * high accuracy, and we didn't miss any events. We can thus 158 * use the TSC value at the transitions to calculate a pretty 159 * good value for the TSC frequencty. 160 */ 161 static inline int pit_verify_msb(unsigned char val) 162 { 163 /* Ignore LSB */ 164 inb(0x42); 165 return inb(0x42) == val; 166 } 167 168 static inline int pit_expect_msb(unsigned char val, u64 *tscp, 169 unsigned long *deltap) 170 { 171 int count; 172 u64 tsc = 0, prev_tsc = 0; 173 174 for (count = 0; count < 50000; count++) { 175 if (!pit_verify_msb(val)) 176 break; 177 prev_tsc = tsc; 178 tsc = rdtsc(); 179 } 180 *deltap = rdtsc() - prev_tsc; 181 *tscp = tsc; 182 183 /* 184 * We require _some_ success, but the quality control 185 * will be based on the error terms on the TSC values. 186 */ 187 return count > 5; 188 } 189 190 /* 191 * How many MSB values do we want to see? We aim for 192 * a maximum error rate of 500ppm (in practice the 193 * real error is much smaller), but refuse to spend 194 * more than 50ms on it. 195 */ 196 #define MAX_QUICK_PIT_MS 50 197 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) 198 199 static unsigned long __maybe_unused quick_pit_calibrate(void) 200 { 201 int i; 202 u64 tsc, delta; 203 unsigned long d1, d2; 204 205 /* Set the Gate high, disable speaker */ 206 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 207 208 /* 209 * Counter 2, mode 0 (one-shot), binary count 210 * 211 * NOTE! Mode 2 decrements by two (and then the 212 * output is flipped each time, giving the same 213 * final output frequency as a decrement-by-one), 214 * so mode 0 is much better when looking at the 215 * individual counts. 216 */ 217 outb(0xb0, 0x43); 218 219 /* Start at 0xffff */ 220 outb(0xff, 0x42); 221 outb(0xff, 0x42); 222 223 /* 224 * The PIT starts counting at the next edge, so we 225 * need to delay for a microsecond. The easiest way 226 * to do that is to just read back the 16-bit counter 227 * once from the PIT. 228 */ 229 pit_verify_msb(0); 230 231 if (pit_expect_msb(0xff, &tsc, &d1)) { 232 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { 233 if (!pit_expect_msb(0xff-i, &delta, &d2)) 234 break; 235 236 /* 237 * Iterate until the error is less than 500 ppm 238 */ 239 delta -= tsc; 240 if (d1+d2 >= delta >> 11) 241 continue; 242 243 /* 244 * Check the PIT one more time to verify that 245 * all TSC reads were stable wrt the PIT. 246 * 247 * This also guarantees serialization of the 248 * last cycle read ('d2') in pit_expect_msb. 249 */ 250 if (!pit_verify_msb(0xfe - i)) 251 break; 252 goto success; 253 } 254 } 255 debug("Fast TSC calibration failed\n"); 256 return 0; 257 258 success: 259 /* 260 * Ok, if we get here, then we've seen the 261 * MSB of the PIT decrement 'i' times, and the 262 * error has shrunk to less than 500 ppm. 263 * 264 * As a result, we can depend on there not being 265 * any odd delays anywhere, and the TSC reads are 266 * reliable (within the error). 267 * 268 * kHz = ticks / time-in-seconds / 1000; 269 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 270 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) 271 */ 272 delta *= PIT_TICK_RATE; 273 delta /= (i*256*1000); 274 debug("Fast TSC calibration using PIT\n"); 275 return delta / 1000; 276 } 277 278 /* Get the speed of the TSC timer in MHz */ 279 unsigned notrace long get_tbclk_mhz(void) 280 { 281 return get_tbclk() / 1000000; 282 } 283 284 static ulong get_ms_timer(void) 285 { 286 return (get_ticks() * 1000) / get_tbclk(); 287 } 288 289 ulong get_timer(ulong base) 290 { 291 return get_ms_timer() - base; 292 } 293 294 ulong notrace timer_get_us(void) 295 { 296 return get_ticks() / get_tbclk_mhz(); 297 } 298 299 ulong timer_get_boot_us(void) 300 { 301 return timer_get_us(); 302 } 303 304 void __udelay(unsigned long usec) 305 { 306 u64 now = get_ticks(); 307 u64 stop; 308 309 stop = now + usec * get_tbclk_mhz(); 310 311 while ((int64_t)(stop - get_ticks()) > 0) 312 #if defined(CONFIG_QEMU) && defined(CONFIG_SMP) 313 /* 314 * Add a 'pause' instruction on qemu target, 315 * to give other VCPUs a chance to run. 316 */ 317 asm volatile("pause"); 318 #else 319 ; 320 #endif 321 } 322 323 static int tsc_timer_get_count(struct udevice *dev, u64 *count) 324 { 325 u64 now_tick = rdtsc(); 326 327 *count = now_tick - gd->arch.tsc_base; 328 329 return 0; 330 } 331 332 static int tsc_timer_probe(struct udevice *dev) 333 { 334 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); 335 336 gd->arch.tsc_base = rdtsc(); 337 338 /* 339 * If there is no clock frequency specified in the device tree, 340 * calibrate it by ourselves. 341 */ 342 if (!uc_priv->clock_rate) { 343 unsigned long fast_calibrate; 344 345 fast_calibrate = try_msr_calibrate_tsc(); 346 if (!fast_calibrate) { 347 fast_calibrate = quick_pit_calibrate(); 348 if (!fast_calibrate) 349 panic("TSC frequency is ZERO"); 350 } 351 352 uc_priv->clock_rate = fast_calibrate * 1000000; 353 } 354 355 return 0; 356 } 357 358 static const struct timer_ops tsc_timer_ops = { 359 .get_count = tsc_timer_get_count, 360 }; 361 362 static const struct udevice_id tsc_timer_ids[] = { 363 { .compatible = "x86,tsc-timer", }, 364 { } 365 }; 366 367 U_BOOT_DRIVER(tsc_timer) = { 368 .name = "tsc_timer", 369 .id = UCLASS_TIMER, 370 .of_match = tsc_timer_ids, 371 .probe = tsc_timer_probe, 372 .ops = &tsc_timer_ops, 373 .flags = DM_FLAG_PRE_RELOC, 374 }; 375