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b3bfcf59 |
| 17-Aug-2022 |
Jianqun Xu <jay.xu@rock-chips.com> |
pinctrl: rockchip: fix iomux set for rk3588 GPIO0_B4-GPIO0_D7
The pin range from GPIO0_B4 to GPIO0_D7 for rk3588 SoCs should set two
registers for iomux, since each of them has 8 bits width.
This p
pinctrl: rockchip: fix iomux set for rk3588 GPIO0_B4-GPIO0_D7
The pin range from GPIO0_B4 to GPIO0_D7 for rk3588 SoCs should set two
registers for iomux, since each of them has 8 bits width.
This patch fixes a issue when reset the iomux from a value from larger
than 8 to a value littler than 8, the high 4 bits should be reset to
'0'.
Change-Id: I48cda1c76bfd9b6546c3b91f511a75ea1e36ce7a
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
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