PCI: add AER dump support

=> pci e
unable to get syscon device for rockchip,pipe-grf
snps pcie3phy FW update! size 8192
pcie@fe280000: PCIe Linking... LTSSM is 0x0
pcie@fe280000: PCIe Link up, LTSSM

PCI: add AER dump support

=> pci e
unable to get syscon device for rockchip,pipe-grf
snps pcie3phy FW update! size 8192
pcie@fe280000: PCIe Linking... LTSSM is 0x0
pcie@fe280000: PCIe Link up, LTSSM is 0x30011
pcie@fe280000: PCIE-0: Link up (Gen1-x2, Bus0)
=> nvme scan
=> pci aer 01.00.0
AER Capability found at offset 0x40
UESta: DLP-- SDES-- TLP-- FCP-- CmpltTO-- CmpltAbrt-- UnxCmplt-- RxOF-- MalfTLP-- ECRC-- UnsupReq-- ACSViol--
UEMsk: DLP-- SDES-- TLP-- FCP-- CmpltTO-- CmpltAbrt-- UnxCmplt-- RxOF-- MalfTLP-- ECRC-- UnsupReq-- ACSViol--
UESvrt: DLP+ SDES- TLP+ FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
CESta: RxErr-- BadTLP-- BadDLLP-- Rollover-- Timeout-- NonFatalErr--
CEMsk: RxErr-- BadTLP-- BadDLLP-- Rollover-- Timeout-- NonFatalErr--
AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-

Change-Id: Ie861fc0f1e9b70468cb27f40fa00458339cd2b4e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

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drivers: pci: Add Rockchip DesignWare based PCIe controller

=> pci enum
PCIe Linking... LTSSM is 0x1
PCIe Link up, LTSSM is 0x230011
PCIE-0: Link up (Gen3-x2, Bus0)

=> pci scan
Scanning PCI devices

drivers: pci: Add Rockchip DesignWare based PCIe controller

=> pci enum
PCIe Linking... LTSSM is 0x1
PCIe Link up, LTSSM is 0x230011
PCIE-0: Link up (Gen3-x2, Bus0)

=> pci scan
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.00.00 0x1d87 0x3566 Bridge device 0x04

=> pci 1
Scanning PCI devices on bus 1
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
01.00.00 0x144d 0xa808 Mass storage controller 0x08

=> nvme scan

=> nvme details
Blk device 0: Optional Admin Command Support:
Namespace Management/Attachment: no
Firmware Commit/Image download: yes
Format NVM: yes
Security Send/Receive: no
Blk device 0: Optional NVM Command Support:
Reservation: yes
Save/Select field in the Set/Get features: yes
Write Zeroes: yes
Dataset Management: yes
Write Uncorrectable: yes
Blk device 0: Format NVM Attributes:
Support Cryptographic Erase: No
Support erase a particular namespace: Yes
Support format a particular namespace: Yes
Blk device 0: LBA Format Support:
Blk device 0: End-to-End DataProtect Capabilities:
As last eight bytes: No
As first eight bytes: No
Support Type3: No
Support Type2: No
Support Type1: No
Blk device 0: Metadata capabilities:
As part of a separate buffer: No
As part of an extended data LBA: No

=> nvme info
Device 0: Vendor: 0x144d Rev: EXD7201Q Prod: S444NA0M384608
Type: Hard Disk
Capacity: 244198.3 MB = 238.4 GB (500118192 x 512)

=> nvme device 0

=> md.l 0x40000000 1
40000000: d08ec033 3...
=> mw.l 0x40000000 0x55aa55aa
=> md.l 0x40000000 1
40000000: 55aa55aa .U.U

=> nvme write 0x40000000 0x0 0x1

nvme write: device 0 block # 0, count 1 ... 1 blocks written: OK

=> md.l 0x44000000 1
44000000: ffffffff ....
=> nvme read 0x44000000 0x0 0x1

nvme read: device 0 block # 0, count 1 ... 1 blocks read: OK

=> md.l 0x44000000 1
44000000: 55aa55aa .U.U

Change-Id: I645dfc7e88722e9948ecb6e1a3a589eb4b420c1f
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

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Drop CONFIG_WINBOND_83C553

This is not used in U-Boot. Drop this option and associated dead code.

Signed-off-by: Simon Glass <sjg@chromium.org>

Merge git://git.denx.de/u-boot-fsl-qoriq

pci: layerscape: move kernel DT fixup to a separate file

To make the layerscape pcie driver clear, move the kernel DT fixup
code from pcie_layerscape.c to pcie_layerscape_fixup.c.

Signed-off-by: Ho

pci: layerscape: move kernel DT fixup to a separate file

To make the layerscape pcie driver clear, move the kernel DT fixup
code from pcie_layerscape.c to pcie_layerscape_fixup.c.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot

pci: mvebu: Add PCIe driver for Armada-8K

This patch adds a driver for the PCIe controller integrated in the
Marvell Armada-8K SoC. This controller is based on the DesignWare
IP core.

The original

pci: mvebu: Add PCIe driver for Armada-8K

This patch adds a driver for the PCIe controller integrated in the
Marvell Armada-8K SoC. This controller is based on the DesignWare
IP core.

The original version was written by Shadi and Yehuda. I ported this
driver to the latest mainline U-Boot version with DM support.

Tested on the Marvell DB-88F8040 Armada-8K eval board.

Signed-off-by: Shadi Ammouri <shadi@marvell.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>

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Merge branch 'master' of git://git.denx.de/u-boot-mips

pci: xilinx: Add a driver for Xilinx AXI to PCIe bridge

This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is

pci: xilinx: Add a driver for Xilinx AXI to PCIe bridge

This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is
mostly a case of implementing PCIe ECAM specification, but with some
quirks about what devices are valid to access.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-dm

dm: pci: video: Convert video and pci_rom to use DM PCI API

Adjust these files to use the driver-model PCI API instead of the legacy
functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-b

dm: pci: video: Convert video and pci_rom to use DM PCI API

Adjust these files to use the driver-model PCI API instead of the legacy
functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

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dm: pci: Use driver model PCI API in auto-config

At present we are using legacy functions even in the auto-configuration code
used by driver model. Add a new pci_auto.c version which uses the correc

dm: pci: Use driver model PCI API in auto-config

At present we are using legacy functions even in the auto-configuration code
used by driver model. Add a new pci_auto.c version which uses the correct
API.

Create a new pci_internal.h header to hold functions that are used within
the PCI subsystem, but are not exported to other drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

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dm: pci: Disable PCI compatibility functions by default

We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hid

dm: pci: Disable PCI compatibility functions by default

We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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dm: pci: Move common auto-config functions to a common file

Some functions will be used by driver model and legacy PCI code. To avoid
duplication, put these in a separate, shared file.

Signed-off-b

dm: pci: Move common auto-config functions to a common file

Some functions will be used by driver model and legacy PCI code. To avoid
duplication, put these in a separate, shared file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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dm: pci: Rename pci_auto.c to pci_auto_old.c

This file should not be used with driver model as it has lots of legacy/
compatibility functions. Rename it to make this clear.

Signed-off-by: Simon Gla

dm: pci: Rename pci_auto.c to pci_auto_old.c

This file should not be used with driver model as it has lots of legacy/
compatibility functions. Rename it to make this clear.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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Merge git://git.denx.de/u-boot-marvell

pci: mvebu: Add PCIe driver

This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.

Besides the driver, this patch also removes the statically defined
PCI MBUS windows. As they are

pci: mvebu: Add PCIe driver

This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.

Besides the driver, this patch also removes the statically defined
PCI MBUS windows. As they are not needed anymore, since this PCIe
driver now creates the windows dynamically.

Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000
PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp
eval board using this Intel E1000 PCIe card in the PCIe 0 slot.

This port was done in cooperation with Anton Schubert.

Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>

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Merge branch 'u-boot/master' into 'u-boot-arm/master'

dm: x86: pci: Add a PCI driver for driver model

Add a simple x86 PCI driver which uses standard functions provided by the
architecture.

Signed-off-by: Simon Glass <sjg@chromium.org>

dm: sandbox: pci: Add a PCI emulation uclass

Since sandbox does not have real devices (unless it borrows those from the
host) it must use emulations. Provide a uclass which permits PCI operations
to

dm: sandbox: pci: Add a PCI emulation uclass

Since sandbox does not have real devices (unless it borrows those from the
host) it must use emulations. Provide a uclass which permits PCI operations
to be passed through to an emulation device.

Signed-off-by: Simon Glass <sjg@chromium.org>

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dm: sandbox: Add a simple PCI driver

Add a driver which can access emulations of devices and make them available
in sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>

dm: pci: Add a uclass for PCI

Add a uclass for PCI controllers and a generic one for PCI devices. Adjust
the 'pci' command and the existing PCI support to work with this new uclass.
Keep most of the

dm: pci: Add a uclass for PCI

Add a uclass for PCI controllers and a generic one for PCI devices. Adjust
the 'pci' command and the existing PCI support to work with this new uclass.
Keep most of the compatibility code in a separate file so that it can be
removed one day.

TODO: Add more header file comments to the new parts of pci.h

Signed-off-by: Simon Glass <sjg@chromium.org>

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dm: pci: Move common PCI functions into their own file

Driver model will share many functions with the existing PCI implementation.
Move these into their own file to avoid duplication and confusion.

dm: pci: Move common PCI functions into their own file

Driver model will share many functions with the existing PCI implementation.
Move these into their own file to avoid duplication and confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>

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Merge branch 'master' of git://git.denx.de/u-boot-tegra

pci: tegra: Add Tegra PCIe driver

Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6

pci: tegra: Add Tegra PCIe driver

Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.

This is based on the Linux kernel driver, originally submitted upstream
by Mike Rapoport.

Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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