UPSTREAM: mtd: nand: lpc32xx slc: disable DMA support in SPL builds

Testing and analysis shows that at the moment LPC32xx NAND SLC driver
can not get PL080 DMA backbone support in SPL build, because

UPSTREAM: mtd: nand: lpc32xx slc: disable DMA support in SPL builds

Testing and analysis shows that at the moment LPC32xx NAND SLC driver
can not get PL080 DMA backbone support in SPL build, because SPL NAND
loaders operate with subpage (ECC step to be precisely) reads, and
this is not supported in the NAND SLC + DMA + hardware ECC calculation
bundle.

The change removes a cautious build time warning and explicitly
disables DMA flavour of the driver for SPL builds, to reduce the
amound of #ifdef sections the code blocks are minimally reorganized.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Change-Id: I9af7057ff579b3afc216038ce959a6f9f3e02279
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 44cdfc0ece20d649ab18690a8020da34137a670b)

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UPSTREAM: mtd: nand: lpc32xx mlc: predefine number of NAND chips to support

Build option CONFIG_SYS_MAX_NAND_CHIPS is used by NXP LPC32xx NAND MLC
driver only, as a preparation for potential removal

UPSTREAM: mtd: nand: lpc32xx mlc: predefine number of NAND chips to support

Build option CONFIG_SYS_MAX_NAND_CHIPS is used by NXP LPC32xx NAND MLC
driver only, as a preparation for potential removal or replacement of
the option the change predefines CONFIG_SYS_MAX_NAND_CHIPS to 1, same
value is used by the single user Work Microwave Work 92105 board, thus
it will be safe now to remove the option as a board specific one.

Change-Id: I970ed8175e95e7a7a15d310b78c9d83f95be4ea3
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a098ce21420e2359042041efaede75a8360c9f42)

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UPSTREAM: nand: atmel: Initialize pmecc smu with correct size

Currently in pmecc_get_sigma(), the code tries to clear the memory
pointed by smu with wrong size 'sizeof(int16_t) * ARRAY_SIZE(smu)'.
S

UPSTREAM: nand: atmel: Initialize pmecc smu with correct size

Currently in pmecc_get_sigma(), the code tries to clear the memory
pointed by smu with wrong size 'sizeof(int16_t) * ARRAY_SIZE(smu)'.
Since smu is actually a pointer, not an array, so ARRAY_SIZE(smu)
does not generate correct size to be cleared.

In fact, GCC 8.1.0 reports a warning against it:

error: division 'sizeof (int16_t * {aka short int *}) / sizeof (int16_t
{aka short int})' does not compute the number of array elements
[-Werror=sizeof-pointer-div]

Fix it by using the correct size.

Change-Id: I9a74b5a51c848cec7b54443449cb00609df00b39
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ed5df0852f56a3512db283010ad7b6e93cba0612)

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UPSTREAM: mtd: nand: spi: Add Gigadevice SPI NAND support

This patch adds support for Gigadevices SPI NAND device to the new SPI
NAND infrastructure in U-Boot. Currently only the 128MiB GD5F1GQ4UC
d

UPSTREAM: mtd: nand: spi: Add Gigadevice SPI NAND support

This patch adds support for Gigadevices SPI NAND device to the new SPI
NAND infrastructure in U-Boot. Currently only the 128MiB GD5F1GQ4UC
device is supported.

Change-Id: I9939a71a038b27bb7250dec0617a0d11e18f03dd
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Jagan Teki <jagan@openedev.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9e5c2a755a6ca5f3931de548f43101d0d18ac003)

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UPSTREAM: mtd: spinand: Add initial support for the MX35LF2GE4AB chip

Add support for the MX35LF2GE4AB chip, which is similar to its cousin
MX35LF1GE4AB, with two planes instead of one.

Change-Id:

UPSTREAM: mtd: spinand: Add initial support for the MX35LF2GE4AB chip

Add support for the MX35LF2GE4AB chip, which is similar to its cousin
MX35LF1GE4AB, with two planes instead of one.

Change-Id: Ib1821e688151f9e9790effc78e7446c6387b3525
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 515d0212615b8b4bbe1e39ccf7946e042dc1bf58)

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UPSTREAM: mtd: spinand: Add initial support for the MX35LF1GE4AB chip

Add minimal support for the MX35LF1GE4AB SPI NAND chip.

Change-Id: Ifb036b16f09086f5cda092c30bb850d1f91668a4
Signed-off-by: Bor

UPSTREAM: mtd: spinand: Add initial support for the MX35LF1GE4AB chip

Add minimal support for the MX35LF1GE4AB SPI NAND chip.

Change-Id: Ifb036b16f09086f5cda092c30bb850d1f91668a4
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6f041ccabb03bea16c2f21f3254dc9c1cb38425c)

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UPSTREAM: mtd: spinand: Add initial support for Winbond W25M02GV

Add support for the W25M02GV chip.

Change-Id: Iad3e56fb79484fe8bd809c74f033ca1cc270c68b
Signed-off-by: Frieder Schrempf <frieder.sch

UPSTREAM: mtd: spinand: Add initial support for Winbond W25M02GV

Add support for the W25M02GV chip.

Change-Id: Iad3e56fb79484fe8bd809c74f033ca1cc270c68b
Signed-off-by: Frieder Schrempf <frieder.schrempf@exceet.de>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 3181c0a622d35bd8e6d4407458e7204d4df5a8c1)

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UPSTREAM: mtd: spinand: Add initial support for Micron MT29F2G01ABAGD

Add a basic driver for Micron SPI NANDs. Only one device is supported
right now, but the driver will be extended to support more

UPSTREAM: mtd: spinand: Add initial support for Micron MT29F2G01ABAGD

Add a basic driver for Micron SPI NANDs. Only one device is supported
right now, but the driver will be extended to support more devices
afterwards.

Change-Id: I00be31e80599565e8bd3c01e17177c6594f5b98b
Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 883d8778ae177172c0a53c018faa39e61f30dea3)

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UPSTREAM: mtd: nand: Add core infrastructure to support SPI NANDs

Add a SPI NAND framework based on the generic NAND framework and the
spi-mem infrastructure.

In its current state, this framework s

UPSTREAM: mtd: nand: Add core infrastructure to support SPI NANDs

Add a SPI NAND framework based on the generic NAND framework and the
spi-mem infrastructure.

In its current state, this framework supports the following features:

- single/dual/quad IO modes
- on-die ECC

Change-Id: Ifdb3001b7570e0e034f7125c4b66053462f2aed2
Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 0a6d6bae03864938f073cc114992c40f2338a155)

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UPSTREAM: mtd: nand: Add core infrastructure to deal with NAND devices

Add an intermediate layer to abstract NAND device interface so that
some logic can be shared between SPI NANDs, parallel/raw NA

UPSTREAM: mtd: nand: Add core infrastructure to deal with NAND devices

Add an intermediate layer to abstract NAND device interface so that
some logic can be shared between SPI NANDs, parallel/raw NANDs,
OneNANDs, ...

Change-Id: I0c2b2e3ddae912756a35aac2741dd1ce8a243b35
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b95db8d33a1e920801816e47ffc5c6f18acce024)

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UPSTREAM: mtd: rename nand into rawnand in Kconfig prompt

Sync the Kconfig raw NAND entry title with the code architecture.

Change-Id: I81c8cfd67b94c67ec6b5e3bf31b0df908c8a9fdb
Signed-off-by: Mique

UPSTREAM: mtd: rename nand into rawnand in Kconfig prompt

Sync the Kconfig raw NAND entry title with the code architecture.

Change-Id: I81c8cfd67b94c67ec6b5e3bf31b0df908c8a9fdb
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 3657b2f4a309ed2e527c805333f9485757912397)

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UPSTREAM: mtd: move NAND files into a raw/ subdirectory

NAND flavors, like serial and parallel, have a lot in common and would
benefit to share code. Let's move raw (parallel) NAND specific code in

UPSTREAM: mtd: move NAND files into a raw/ subdirectory

NAND flavors, like serial and parallel, have a lot in common and would
benefit to share code. Let's move raw (parallel) NAND specific code in a
raw/ subdirectory, to ease the addition of a core file in nand/ and the
introduction of a spi/ subdirectory specific to SPI NANDs.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Change-Id: Ibb56f85620c4798fb579be3e4e30438963b7c48b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a430fa06a4ac50e785fdbfb7f43c3cb14b35619c)

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UPSTREAM: mtd: Fallback to ->_read/write_oob() when ->_read/write() is missing

Some MTD sublayers/drivers are implementing ->_read/write_oob() and
provide dummy wrappers for their ->_read/write() im

UPSTREAM: mtd: Fallback to ->_read/write_oob() when ->_read/write() is missing

Some MTD sublayers/drivers are implementing ->_read/write_oob() and
provide dummy wrappers for their ->_read/write() implementations.
Let the core handle this case instead of duplicating the logic.

Change-Id: I7276effeba2885da48ab4834e272c51a258588dd
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 596cf083da34c2007f8ec760c8b077f6f28ee655)

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UPSTREAM: fix: nand: pxa3xx: Add WA for eliminating flash ready timeout

add delay before processing the status flags in pxa3xx_nand_irq().

Change-Id: I06cb7459b9f1127ce8d66b04fdaedc026b4c77da
Signe

UPSTREAM: fix: nand: pxa3xx: Add WA for eliminating flash ready timeout

add delay before processing the status flags in pxa3xx_nand_irq().

Change-Id: I06cb7459b9f1127ce8d66b04fdaedc026b4c77da
Signed-off-by: David Sniatkiwicz <davidsn@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
c: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e76afd84095a10e7cd9d8ee6b74ed94941e5f4f8)

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UPSTREAM: nand: pxa3xx: Add support for 8KB page 4 and 8 bit ECC NAND

Add support for NAND chips with 8KB page, 4 and 8 bit ECC (ONFI).

Change-Id: I9fbcd1b11f5ef22d352730b44be5f84cacc255aa
Signed-o

UPSTREAM: nand: pxa3xx: Add support for 8KB page 4 and 8 bit ECC NAND

Add support for NAND chips with 8KB page, 4 and 8 bit ECC (ONFI).

Change-Id: I9fbcd1b11f5ef22d352730b44be5f84cacc255aa
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b7b3f2c8bbf346b29f877b61d7e2b12a877b01d0)

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UPSTREAM: nand: pxa3xx: cosmetic: add comments to the timing layout structures

Add comments with timing parameter names and some details about
nand layout fileds.
Remove unneeded definition.

Change

UPSTREAM: nand: pxa3xx: cosmetic: add comments to the timing layout structures

Add comments with timing parameter names and some details about
nand layout fileds.
Remove unneeded definition.

Change-Id: I82d550b47e92bf0ec3c4aaadd6bd0a537fb96ce5
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e9a0777f851c3ffa5ece59921427d89bab1d7506)

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UPSTREAM: fix: nand: Replace hardcoded page chunk size with calculated one

Replace the hardcoded value of page chink with value that
depends on flash page size and ECC strength.
This fixes nand acce

UPSTREAM: fix: nand: Replace hardcoded page chunk size with calculated one

Replace the hardcoded value of page chink with value that
depends on flash page size and ECC strength.
This fixes nand access errors for 2K page flashes with 8-bit ECC.
Move the initial flash commannd function assignment past the ECC
structures initialization for eliminating usage of hardcoded page
chunk size value.

Change-Id: I3d75d6b65012ca38572d75e505bb085b643830d6
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 2057eb0b163ac31fee00ae6ef9e8e27dcca65fd5)

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UPSTREAM: mtd: nand: pxa3xx: add support for Toshiba flash

Add timings and device ID for Toshiba TC58NVG1S3HTA00 flash

Change-Id: I7aa6eb7f84b5063e5497355058cbe3bc00519f2a
Signed-off-by: Konstantin

UPSTREAM: mtd: nand: pxa3xx: add support for Toshiba flash

Add timings and device ID for Toshiba TC58NVG1S3HTA00 flash

Change-Id: I7aa6eb7f84b5063e5497355058cbe3bc00519f2a
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b0d7c106c9703498f12bb1254b02574c803874a0)

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UPSTREAM: mtd: nand: pxa3xx: add support for 2KB 8-bit flash

Add support for 2KB page 8-bit ECC strength flash layout

Change-Id: I3a4f2712c7107be83d2c63adc2c62841f4dac56d
Signed-off-by: Victor Axel

UPSTREAM: mtd: nand: pxa3xx: add support for 2KB 8-bit flash

Add support for 2KB page 8-bit ECC strength flash layout

Change-Id: I3a4f2712c7107be83d2c63adc2c62841f4dac56d
Signed-off-by: Victor Axelrod <victora@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ac56a3b30cc74f2c9dd667705e756ff5f5aeda0f)

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UPSTREAM: mtd: nand: pxa3xx: Fix READOOB implementation

In the current driver, OOB bytes are accessed in raw mode, and when a
page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the

UPSTREAM: mtd: nand: pxa3xx: Fix READOOB implementation

In the current driver, OOB bytes are accessed in raw mode, and when a
page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the
driver must read the whole spare area (64 bytes in case of a 2k page,
16 bytes for a 512 page). The driver was only reading the free OOB
bytes, which was leaving some unread data in the FIFO and was somehow
leading to a timeout.

We could patch the driver to read ->spare_size + ->ecc_size instead of
just ->spare_size when READOOB is requested, but we'd better make
in-band and OOB accesses consistent.
Since the driver is always accessing in-band data in non-raw mode (with
the ECC engine enabled), we should also access OOB data in this mode.
That's particularly useful when using the BCH engine because in this
mode the free OOB bytes are also ECC protected.

Fixes: 43bcfd2bb24a ("mtd: nand: pxa3xx: Add driver-specific ECC BCH support")
Cc: stable@vger.kernel.org
Change-Id: I4b53b3f4fd84e58ca78d01492a3768ba5ba4eaa0
Reported-by: Sean Nyekjær <sean.nyekjaer@prevas.dk>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit f3d235702de09622a542ba2830882d23e2dfee1f)

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UPSTREAM: mtd: nand: pxa3xx_nand: add support for partial chunks

This commit is needed to properly support the 8-bits ECC configuration
with 4KB pages.

When pages larger than 2 KB are used on platf

UPSTREAM: mtd: nand: pxa3xx_nand: add support for partial chunks

This commit is needed to properly support the 8-bits ECC configuration
with 4KB pages.

When pages larger than 2 KB are used on platforms using the PXA3xx
NAND controller, the reading/programming operations need to be split
in chunks of 2 KBs or less because the controller FIFO is limited to
about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to
this requirement, the data layout on NAND is a bit strange, with ECC
interleaved with data, at the end of each chunk.

When a 4-bits ECC configuration is used with 4 KB pages, the physical
data layout on the NAND looks like this:

| 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC |

So the data chunks have an equal size, 2080 bytes for each chunk,
which the driver supports properly.

When a 8-bits ECC configuration is used with 4KB pages, the physical
data layout on the NAND looks like this:

| 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 64 spare | 30 ECC |

So, the spare area is stored in its own chunk, which has a different
size than the other chunks. Since OOB is not used by UBIFS, the initial
implementation of the driver has chosen to not support reading this
additional "spare" chunk of data.

Unfortunately, Marvell has chosen to store the BBT signature in the
OOB area. Therefore, if the driver doesn't read this spare area, Linux
has no way of finding the BBT. It thinks there is no BBT, and rewrites
one, which U-Boot does not recognize, causing compatibility problems
between the bootloader and the kernel in terms of NAND usage.

To fix this, this commit implements the support for reading a partial
last chunk. This support is currently only useful for the case of 8
bits ECC with 4 KB pages, but it will be useful in the future to
enable other configurations such as 12 bits and 16 bits ECC with 4 KB
pages, or 8 bits ECC with 8 KB pages, etc. All those configurations
have a "last" chunk that doesn't have the same size as the other
chunks.

In order to implement reading of the last chunk, this commit:

- Adds a number of new fields to the pxa3xx_nand_info to describe how
many full chunks and how many chunks we have, the size of full
chunks and partial chunks, both in terms of data area and spare
area.

- Fills in the step_chunk_size and step_spare_size variables to
describe how much data and spare should be read/written for the
current read/program step.

- Reworks the state machine to accommodate doing the additional read
or program step when a last partial chunk is used.

This commit is taken from Linux:
'commit c2cdace755b'
("mtd: nand: pxa3xx_nand: add support for partial chunks")

Change-Id: I63a98c133cbadb1cfe1b1919bf08182e5ea99c47
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b47f677931b2255d0d454e100590e94f0dd97f55)

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UPSTREAM: mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan

This commit simplifies the initial configuration performed
by pxa3xx_nand_scan. No functionality change is intended.

This commit is taken from

UPSTREAM: mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan

This commit simplifies the initial configuration performed
by pxa3xx_nand_scan. No functionality change is intended.

This commit is taken from Linux:
'commit 154f50fbde53'
("mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan")

Change-Id: I72a34c2a18addb5a96b98fa5799bc9391a934d26
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 7efd95eacf790714e70415cbe290056fedc33f82)

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UPSTREAM: mtd: pxa3xx_nand: Fix initial controller configuration

The Data Flash Control Register (NDCR) contains two types
of parameters: those that are needed for device identification,
and those t

UPSTREAM: mtd: pxa3xx_nand: Fix initial controller configuration

The Data Flash Control Register (NDCR) contains two types
of parameters: those that are needed for device identification,
and those that can only be set after device identification.

Therefore, the driver can't set them all at once and instead
needs to configure the first group before nand_scan_ident()
and the second group later.

Let's split pxa3xx_nand_config in two halves, and set the
parameters that depend on the device geometry once this is known.

This commit is taken from Linux:
'commit 66e8e47eae65'
("mtd: pxa3xx_nand: Fix initial controller configuration")

Change-Id: I1be50c463d38627c0ed43258c59ca9624d56912e
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b87ae6f587e44e3974e41bd80dbc628540211604)

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UPSTREAM: mtd: pxa3xx_nand: Increase the initial chunk size

The chunk size represents the size of the data chunks, which
is used by the controllers that allow to split transferred data.

However, th

UPSTREAM: mtd: pxa3xx_nand: Increase the initial chunk size

The chunk size represents the size of the data chunks, which
is used by the controllers that allow to split transferred data.

However, the initial chunk size is used in a non-split way,
during device identification. Therefore, it must be large enough
for all the NAND commands issued during device identification.
This includes NAND_CMD_PARAM which was recently changed to
transfer up to 2048 bytes (for the redundant parameter pages).

Thus, the initial chunk size should be 2048 as well.

On Armada 370/XP platforms (NFCv2) booted without the keep-config
devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM
command:

[..]
pxa3xx-nand f10d0000.nand: This platform can't do DMA on this device
pxa3xx-nand f10d0000.nand: Wait time out!!!
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38
nand: Micron MT29F8G08ABABAWP
nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224

This commit is taken from Linux:
'commit c7f00c29aa8'
("mtd: pxa3xx_nand: Increase the initial chunk size")

Change-Id: I7bcf3042a0567171d0dc0a90bf3d15c821914cd1
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6bbe7f681feac91fc03a4dc2e88bc0d9391bfaa8)

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UPSTREAM: nand: pxa3xx: Increase READ_ID buffer and make the size static

The read ID count should be made as large as the maximum READ_ID size,
so there's no need to have dynamic size. This commit s

UPSTREAM: nand: pxa3xx: Increase READ_ID buffer and make the size static

The read ID count should be made as large as the maximum READ_ID size,
so there's no need to have dynamic size. This commit sets the hardware
maximum read ID count, which should be more than enough on all cases.
Also, we get rid of the read_id_bytes, and use a macro instead.

This commit is taken from Linux:
'commit b226eca2088'
("nand: pxa3xx: Increase READ_ID buffer and make the size static")

Change-Id: If5d3398463cb409d7b62f9d7f23dd29ea77efe7a
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 94488612cb21e51b772e3b616c8f1acfe2d0961c)

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