mtd: spinand: macronix: Support more devices

MX35UF4GE4AD

Change-Id: I61f5cb6827800247cffe58dbbcbd2068fc526943
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: macronix: Support more devices

Change-Id: Ib120e21ecaf9b3a43a1bba9c2a189bae864113b7
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: macronix: Support more devices

MX35LF1G24AD,MX35LF2G24AD,MX35LF4G24AD,MX31LF1GE4BC,
MX31UF1GE4BC,MX35LF2G14AC,MX35UF4G24AD,MX35UF4GE4AD,
MX35UF2G14AC,MX35UF2G24AD,MX35UF2GE4AD,MX35UF1G

mtd: spinand: macronix: Support more devices

MX35LF1G24AD,MX35LF2G24AD,MX35LF4G24AD,MX31LF1GE4BC,
MX31UF1GE4BC,MX35LF2G14AC,MX35UF4G24AD,MX35UF4GE4AD,
MX35UF2G14AC,MX35UF2G24AD,MX35UF2GE4AD,MX35UF1G14AC,
MX35UF1G24AD,MX35UF1GE4AD,MX35UF1GE4AC

Change-Id: If04e442cbcd7d1bad4116e175f0a75834d968e13
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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mtd: spinand: rework detect procedure for different READ_ID operation

Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte

mtd: spinand: rework detect procedure for different READ_ID operation

Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E
3. opcode + 1 dummy byte. Found in other currently supported chips.

Original implementation was for variant 1 and let detect function
of chips with variant 2 and 3 to ignore the first byte. This isn't
robust:

1. For chips of variant 2, if SPI master doesn't keep MOSI low
during read, chip will get a random id offset, and the entire id
buffer will shift by that offset, causing detect failure.

2. For chips of variant 1, if it happens to get a devid that equals
to manufacture id of variant 2 or 3 chips, it'll get incorrectly
detected.

This patch reworks detect procedure to address problems above. New
logic do detection for all variants separatedly, in 1-2-3 order.
Since all current detect methods do exactly the same id matching
procedure, unify them into core.c and remove detect method from
manufacture_ops.

Link: https://lore.kernel.org/linux-mtd/20200208074439.146296-1-gch981213@gmail.com

Change-Id: Ib06417c8e8c7e9d58be1eb3549468bfcbd74350d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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mtd: spinand: macronix: Fix ECC Status Read

commit f4cb4d7b46f6409382fd981eec9556e1f3c1dc5d linux upstream

The datasheet specifies the upper four bits are reserved.
Testing on real hardware shows t

mtd: spinand: macronix: Fix ECC Status Read

commit f4cb4d7b46f6409382fd981eec9556e1f3c1dc5d linux upstream

The datasheet specifies the upper four bits are reserved.
Testing on real hardware shows that these bits can indeed be nonzero.

Signed-off-by: Emil Lenngren <emil.lenngren@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Change-Id: I061f499427ffdb09d76132db7796cc4b04a5e388

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mtd: spinand: Supoprt new MXIC devices

MX35UF1GE4AC, MX35UF2GE4AC

Change-Id: I064e9116c565e2ea3b92432e9c68864d47a7567c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: Add initial support for the MX35LF4GE4AD

Change-Id: Ib1228650e76dc82bc86fb28472616d0fefb269bf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: Add initial support for the MX35LF2GE4AD

Change-Id: Iab488487f9937d31cf419757988a4152f359e62b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

UPSTREAM: mtd: Rename free() to rfree()

This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Change-Id:

UPSTREAM: mtd: Rename free() to rfree()

This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Change-Id: I2718843dd4646b7450c36e84cc16e6440c718959
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8d38a8459b0de45f5ff41f3e11c278a5cf395fd0)

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UPSTREAM: mtd: spinand: Add initial support for the MX35LF2GE4AB chip

Add support for the MX35LF2GE4AB chip, which is similar to its cousin
MX35LF1GE4AB, with two planes instead of one.

Change-Id:

UPSTREAM: mtd: spinand: Add initial support for the MX35LF2GE4AB chip

Add support for the MX35LF2GE4AB chip, which is similar to its cousin
MX35LF1GE4AB, with two planes instead of one.

Change-Id: Ib1821e688151f9e9790effc78e7446c6387b3525
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 515d0212615b8b4bbe1e39ccf7946e042dc1bf58)

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UPSTREAM: mtd: spinand: Add initial support for the MX35LF1GE4AB chip

Add minimal support for the MX35LF1GE4AB SPI NAND chip.

Change-Id: Ifb036b16f09086f5cda092c30bb850d1f91668a4
Signed-off-by: Bor

UPSTREAM: mtd: spinand: Add initial support for the MX35LF1GE4AB chip

Add minimal support for the MX35LF1GE4AB SPI NAND chip.

Change-Id: Ifb036b16f09086f5cda092c30bb850d1f91668a4
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6f041ccabb03bea16c2f21f3254dc9c1cb38425c)

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