mtd: spinand: GigaDevice: Support new device GD5F1GM9UEYIGY

Change-Id: Ice3bf37031eaf0a88f9bd96e2c4b7dbe79e665cd
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: gigadevcie: Add 3rd flash id for GD5F1GQ5RExxG

Add 3rd flash id for GD5F1GQ5RExxG to make distinguish with
F50L2G41KA.

Change-Id: I0b789c0a42305a3e12595103794015b715bf4cf8
Signed-off-

mtd: spinand: gigadevcie: Add 3rd flash id for GD5F1GQ5RExxG

Add 3rd flash id for GD5F1GQ5RExxG to make distinguish with
F50L2G41KA.

Change-Id: I0b789c0a42305a3e12595103794015b715bf4cf8
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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mtd: spinand: gigadevice: Sync with kernel

Change-Id: Idfee7fa35c480471ea5a3098d984e89058d56fcf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: gigadevice: Fix GD5F1GQ5UExxG data io strength to 25%

It has been verified on several RK development board that GD5F1GQ5UExxG
default driving strength has an obvious overshoot.

Change

mtd: spinand: gigadevice: Fix GD5F1GQ5UExxG data io strength to 25%

It has been verified on several RK development board that GD5F1GQ5UExxG
default driving strength has an obvious overshoot.

Change-Id: I6a7421e1ef8ef3e9ff219080239696d38095fe54
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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mtd: spinand: Support new devices

GD5F1GM7UxG

Change-Id: Id95ee80a4edb0c315c65d3abb0eccc1cb7691b03
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: gigadevice: Support more devices

GD5F1GQ4xA,GD5F2GQ4xA,GD5F4GQ4xA,GD5F4GQ4RC,GD5F4GQ4UC,GD5F1GQ4UFxxG

Change-Id: I5413308c168092a10790415c914e5e8066856caa
Signed-off-by: Jon Lin <jon.

mtd: spinand: gigadevice: Support more devices

GD5F1GQ4xA,GD5F2GQ4xA,GD5F4GQ4xA,GD5F4GQ4RC,GD5F4GQ4UC,GD5F1GQ4UFxxG

Change-Id: I5413308c168092a10790415c914e5e8066856caa
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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mtd: spinand: Support new devices

GD5F2GM7RxG, GD5F2GM7UxG

Change-Id: I6b5162197dc8671b023d78c0a1e406906e936f49
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: rework detect procedure for different READ_ID operation

Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte

mtd: spinand: rework detect procedure for different READ_ID operation

Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E
3. opcode + 1 dummy byte. Found in other currently supported chips.

Original implementation was for variant 1 and let detect function
of chips with variant 2 and 3 to ignore the first byte. This isn't
robust:

1. For chips of variant 2, if SPI master doesn't keep MOSI low
during read, chip will get a random id offset, and the entire id
buffer will shift by that offset, causing detect failure.

2. For chips of variant 1, if it happens to get a devid that equals
to manufacture id of variant 2 or 3 chips, it'll get incorrectly
detected.

This patch reworks detect procedure to address problems above. New
logic do detection for all variants separatedly, in 1-2-3 order.
Since all current detect methods do exactly the same id matching
procedure, unify them into core.c and remove detect method from
manufacture_ops.

Link: https://lore.kernel.org/linux-mtd/20200208074439.146296-1-gch981213@gmail.com

Change-Id: Ib06417c8e8c7e9d58be1eb3549468bfcbd74350d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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mtd: spinand: Support new device

GD5FxGQ4UExxH

Change-Id: I3f3eeba5a2a9e622ff25b5e3f6a73533d25315cd
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: Support new device

GD5F1GQ4UExxH

Change-Id: I5a156f568aea291ca8219ef86750d1a1d88666aa
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: Support GD5F4GQ6UExxG

Change-Id: Ib72399ca0166ec82fdaf900ac51059076c155de3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: Support GD5F1GQ5UExxG

Change-Id: I5f494ce09eed8c28bd2cb10bac5ec7d9113bac50
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: Fix the way to detect gigadevice id

Parts of esmt devices are the same MFR id, and it's
reasonable.

Change-Id: I245c66ebd734ebabe89d8a6792446b80b76dd0e3
Signed-off-by: Jon Lin <jon.li

mtd: spinand: Fix the way to detect gigadevice id

Parts of esmt devices are the same MFR id, and it's
reasonable.

Change-Id: I245c66ebd734ebabe89d8a6792446b80b76dd0e3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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mtd: spinand: Support GD5F2GQ4UBxxG

Change-Id: Ia3e340ae8b86c282953f94c16b801414218818bf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

UPSTREAM: mtd: Rename free() to rfree()

This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Change-Id:

UPSTREAM: mtd: Rename free() to rfree()

This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Change-Id: I2718843dd4646b7450c36e84cc16e6440c718959
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8d38a8459b0de45f5ff41f3e11c278a5cf395fd0)

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Merge branch 'next-dev' into thunder-boot

mtd: spinand: support GD5F2GQ4UExxG

Change-Id: If7b0c17129b9a914fc6854959cf074b33b876a5e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: Fix GD5F1GQ4UExxG flash info table QE bit flag

Change-Id: Id55ae1dad8798e9c607d76831dc3309882227b3e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

UPSTREAM: mtd: spinand: Sync GigaDevice GD5F1GQ4UExxG with latest Linux version

This patch sync's the U-Boot SPI NAND GigaDevice GD5F1GQ4UExxG support
with the latest Linux version (v5.0-rc3) plus t

UPSTREAM: mtd: spinand: Sync GigaDevice GD5F1GQ4UExxG with latest Linux version

This patch sync's the U-Boot SPI NAND GigaDevice GD5F1GQ4UExxG support
with the latest Linux version (v5.0-rc3) plus the chip supported posted
on the MTD list. Only the currently in U-Boot available chip is
supported with this sync.

The changes for the GD5F1GQ4UExxG are:
- Name of NAND device changed to better reflect the real part
- OOB layout changed to only reserve 1 byte for BBT
- Use ECC caps 8bits/512bytes instead of 8bits/2048bytes
- Enhanced ecc_get_status() function to determine and report
a more fine grained bit error status

Change-Id: Ia0f8ea6e9c19aec57628ea3217128c389c1375c1
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Boris Brezillon <bbrezillon@kernel.org>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d67fb265d1c071c6475fd97d01787b4c961516d5)

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UPSTREAM: mtd: nand: spi: Add Gigadevice SPI NAND support

This patch adds support for Gigadevices SPI NAND device to the new SPI
NAND infrastructure in U-Boot. Currently only the 128MiB GD5F1GQ4UC
d

UPSTREAM: mtd: nand: spi: Add Gigadevice SPI NAND support

This patch adds support for Gigadevices SPI NAND device to the new SPI
NAND infrastructure in U-Boot. Currently only the 128MiB GD5F1GQ4UC
device is supported.

Change-Id: I9939a71a038b27bb7250dec0617a0d11e18f03dd
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Jagan Teki <jagan@openedev.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9e5c2a755a6ca5f3931de548f43101d0d18ac003)

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