mtd: spinand: foresee: Support new device F35SQB002G

Change-Id: Ide047652d0fc18ef03ff8565b6aba3dbfb126564
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: foresee: Support new device F35SQB004G

Change-Id: I08186f5b31b80de91778aeff61de37d58e736e1d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: foresee: Support new device F35UQA002G-WWT

Change-Id: I54177723afb4ca91b79d20e5fd073608f0a5bd82
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: foresee: Support new device F35UQA002G-WWT

Change-Id: I440a907ae4c5d7f23a2a708bb52e489f3fcc8ec0
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: foresee: Fix the way to program load cache

There are many restrictions on the use of the foresee devices Program
Load Random Data (84H), for example it's not allow after a block erase.

mtd: spinand: foresee: Fix the way to program load cache

There are many restrictions on the use of the foresee devices Program
Load Random Data (84H), for example it's not allow after a block erase.

Change-Id: Iafe8971fcbf2fa52a23c2e381bf9c979842607a1
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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mtd: spinand: Support new device

F35SQA512M, F35UQA512M

Change-Id: I01e9e51c6e13f01c49637d9d2607a12bb524190f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: Support new device

F35SQA002G

Change-Id: I31f046dfb537caee9472de6034531f70973f8fea
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: rework detect procedure for different READ_ID operation

Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte

mtd: spinand: rework detect procedure for different READ_ID operation

Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E
3. opcode + 1 dummy byte. Found in other currently supported chips.

Original implementation was for variant 1 and let detect function
of chips with variant 2 and 3 to ignore the first byte. This isn't
robust:

1. For chips of variant 2, if SPI master doesn't keep MOSI low
during read, chip will get a random id offset, and the entire id
buffer will shift by that offset, causing detect failure.

2. For chips of variant 1, if it happens to get a devid that equals
to manufacture id of variant 2 or 3 chips, it'll get incorrectly
detected.

This patch reworks detect procedure to address problems above. New
logic do detection for all variants separatedly, in 1-2-3 order.
Since all current detect methods do exactly the same id matching
procedure, unify them into core.c and remove detect method from
manufacture_ops.

Link: https://lore.kernel.org/linux-mtd/20200208074439.146296-1-gch981213@gmail.com

Change-Id: Ib06417c8e8c7e9d58be1eb3549468bfcbd74350d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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mtd: spinand: Support new devices

FS35SQA001C

Change-Id: I6aef0cdb2a6151f459aee7c80d67752c0c8ad7f5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: Support new devices

FS35ND02G-S3Y2, FS35ND04G-S2Y2

Change-Id: Idc74c823fc707ba4dbeac359c4f6ca0a7e3ee778
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spinand: Add foresee devices

Change-Id: I115ea19030edc2e83e877621f055555b481f98db
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>