irq: gpio-v2: Fix irq unmask

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I00241019a12bd00b24588ba935847f87a3e4d5e5

irq: gpio: Support GPIO id in neither aliases nor node name

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If71c79c7cab8cbf9cd22d3e19856d159dbea4a71

irq: v2: Fix read error

There is not high/low register.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic83d7508ab4dba87778773984c8ccbbd2215e380

irq: use commmon name for read and write operation

It maybe i2c and spi interface, etc.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I320dd67289f42e75515ae247f67d12cc4167347c

irq: generic: use common API

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6ffa9ec4de3406924aa4b9741ac4318deb98c05e

irq: irq-gpio-switch: correct usage of strstr()

Fix gpio interrupt register with wrong gpio bank.

(Fixes: 8db677370c irq: irq-gpio-switch: add gpio alias name support)

Signed-off-by: Joseph Chen <

irq: irq-gpio-switch: correct usage of strstr()

Fix gpio interrupt register with wrong gpio bank.

(Fixes: 8db677370c irq: irq-gpio-switch: add gpio alias name support)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ia60e55a134cfab19ed015796486417e0699bd087

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irq: irq-gpio-switch: add gpio alias name support

Before the patch, we get gpio index(0,1,2..) depends on gpio
fdt node name, such as: gpio0@..., gpio1@..., etc.

But from RK3568, we add gpio alias

irq: irq-gpio-switch: add gpio alias name support

Before the patch, we get gpio index(0,1,2..) depends on gpio
fdt node name, such as: gpio0@..., gpio1@..., etc.

But from RK3568, we add gpio alias to indicate gpio index
information and index is removed from gpio node name, ie:
gpio@fdd60000, gpio@fe740000, etc.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I56e45941f9572fbc6a5a5916896e12f6eff9dcf3

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irq: gicv3: use cpu interface system registers for gicc read/write

RK3568 only support cpu interface system registers access.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie89380e4

irq: gicv3: use cpu interface system registers for gicc read/write

RK3568 only support cpu interface system registers access.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie89380e49ee61afe57560dcc4eba6233f2aca3f2

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irq: use CONFIG_ROCKCHIP_GPIO_V2 instead of CONFIG_IRQ2GPIO_V2

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Id8b232efce483501053bcbd779a444d395c061fc

irq: gicv3: Enables Group 1 interrupts for the current Security state

When a CPU enters a low power state, the registers ICC_IGRPEN1_EL1 is lost.
It need to re-initialise.

Signed-off-by: shengfei X

irq: gicv3: Enables Group 1 interrupts for the current Security state

When a CPU enters a low power state, the registers ICC_IGRPEN1_EL1 is lost.
It need to re-initialise.

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I62d9eed2b29190134d95ebd153f21aa764c4ab3b

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drivers: irq: add irq to gpio v2 transfer support

Some platform with new GPIO IP implements the low/high
registers with write mask. This configure handles it.

Signed-off-by: Joseph Chen <chenjh@roc

drivers: irq: add irq to gpio v2 transfer support

Some platform with new GPIO IP implements the low/high
registers with write mask. This configure handles it.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I855357d29e7fba072b867c06a31a049462ebf6ff

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irq: virq: add parent irq enable/disable management

- disable virq chip by default;
- fix bank->use_count little than 0;

Change-Id: I69aa07cc2924dab40eea6524588869361ad8cf66
Signed-off-by: Joseph C

irq: virq: add parent irq enable/disable management

- disable virq chip by default;
- fix bank->use_count little than 0;

Change-Id: I69aa07cc2924dab40eea6524588869361ad8cf66
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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irq: gicv2: fix GIC not response to USB OTG IRQ

It handles the issue when the bootflow without Miniloader,
i.e. Maskrom => Trust(optional) => U-Boot.

Change-Id: I445225d5cce9abd2117ef468f15774e3fa5

irq: gicv2: fix GIC not response to USB OTG IRQ

It handles the issue when the bootflow without Miniloader,
i.e. Maskrom => Trust(optional) => U-Boot.

Change-Id: I445225d5cce9abd2117ef468f15774e3fa57e16d
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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irq: add "dump_irqs" command support

Change-Id: Ia20bc3b0f4dc600f311ba3de0e75714b5d4c002c
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

irq: add trigger count and enable/disable stat

Change-Id: I3f29c4e3e420be0fe545a2f55f238345a17eaa6a
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

irq: add irq_handler_enable_suspend_only() interface

Change-Id: I3cda4c3a4ce5928be32eaa8b65ccd4e16946c116
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

irq: add virq irq-chip support

This patch support the device to add its interrupt controller as "irq chip"
into generic interrupt framework, the other driver can request its child
interrupt like a r

irq: add virq irq-chip support

This patch support the device to add its interrupt controller as "irq chip"
into generic interrupt framework, the other driver can request its child
interrupt like a real hardware irq.

Example for PMIC:
GIC-\
|- ...
|- GPIO-\
|- ...
|- PMIC-\
|_ virq_0
|_ virq_1
|_ virq_2
|...
|_ virq_n

Change-Id: I17716f3db494a85fc22b23ff18042771a6116da8
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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irq: clean up code

Change-Id: I51c2713b7c42fa798fee6971a2c91d867042ef70
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>