| ef87cab6 | 05-Sep-2014 |
York Sun <yorksun@freescale.com> |
driver/ddr/fsl: Add support of overriding chip select write leveling
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If
driver/ddr/fsl: Add support of overriding chip select write leveling
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun <yorksun@freescale.com>
show more ...
|
| 5cb27c5d | 05-Sep-2014 |
York Sun <yorksun@freescale.com> |
driver/ddr/freescale: Fix DDR3 driver for ARM
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun <yo
driver/ddr/freescale: Fix DDR3 driver for ARM
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun <yorksun@freescale.com>
show more ...
|
| aade2004 | 17-Apr-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
mpc85xx/t104x: Add deep sleep framework support
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like
mpc85xx/t104x: Add deep sleep framework support
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
show more ...
|
| 6b9e309a | 10-Feb-2014 |
York Sun <yorksun@freescale.com> |
Driver/ddr: Add support of different DDR base address
DDR base address has been the same from the view of core and DDR
controllers. This has changed for Freescale ARM-based SoCs. Controllers
setup D
Driver/ddr: Add support of different DDR base address
DDR base address has been the same from the view of core and DDR
controllers. This has changed for Freescale ARM-based SoCs. Controllers
setup DDR memory in a contiguous space and cores view it at separated
locations.
Signed-off-by: York Sun <yorksun@freescale.com>
show more ...
|
| 00ec3fd2 | 28-Oct-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: Update DDR driver to allow non-zero base address
The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.
Signed-off-by
Driver/DDR: Update DDR driver to allow non-zero base address
The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.
Signed-off-by: York Sun <yorksun@freescale.com>
show more ...
|
| d4263b8a | 03-Jun-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Extend DDR registers' fields
Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR cont
powerpc/mpc8xxx: Extend DDR registers' fields
Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.
TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit c360ceac.
Signed-off-by: York Sun <yorksun@freescale.com>
show more ...
|