1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <asm/fsl_errata.h> 23 #include <asm/fsl_law.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/fsl_srio.h> 26 #include <fsl_usb.h> 27 #include <hwconfig.h> 28 #include <linux/compiler.h> 29 #include "mp.h" 30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 31 #include <nand.h> 32 #include <errno.h> 33 #endif 34 35 #include "../../../../drivers/block/fsl_sata.h" 36 #ifdef CONFIG_U_QE 37 #include "../../../../drivers/qe/qe.h" 38 #endif 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 43 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) 44 { 45 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 46 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); 47 48 /* Increase Disconnect Threshold by 50mV */ 49 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 50 INC_DCNT_THRESHOLD_50MV; 51 /* Enable programming of USB High speed Disconnect threshold */ 52 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 53 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); 54 55 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); 56 /* Increase Disconnect Threshold by 50mV */ 57 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 58 INC_DCNT_THRESHOLD_50MV; 59 /* Enable programming of USB High speed Disconnect threshold */ 60 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 61 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); 62 #else 63 64 u32 temp = 0; 65 u32 status = in_be32(&usb_phy->status1); 66 67 u32 squelch_prog_rd_0_2 = 68 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) 69 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 70 71 u32 squelch_prog_rd_3_5 = 72 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) 73 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 74 75 setbits_be32(&usb_phy->config1, 76 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); 77 setbits_be32(&usb_phy->config2, 78 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); 79 80 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; 81 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 82 83 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; 84 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 85 #endif 86 } 87 #endif 88 89 90 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 91 extern qe_iop_conf_t qe_iop_conf_tab[]; 92 extern void qe_config_iopin(u8 port, u8 pin, int dir, 93 int open_drain, int assign); 94 extern void qe_init(uint qe_base); 95 extern void qe_reset(void); 96 97 static void config_qe_ioports(void) 98 { 99 u8 port, pin; 100 int dir, open_drain, assign; 101 int i; 102 103 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 104 port = qe_iop_conf_tab[i].port; 105 pin = qe_iop_conf_tab[i].pin; 106 dir = qe_iop_conf_tab[i].dir; 107 open_drain = qe_iop_conf_tab[i].open_drain; 108 assign = qe_iop_conf_tab[i].assign; 109 qe_config_iopin(port, pin, dir, open_drain, assign); 110 } 111 } 112 #endif 113 114 #ifdef CONFIG_CPM2 115 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 116 { 117 int portnum; 118 119 for (portnum = 0; portnum < 4; portnum++) { 120 uint pmsk = 0, 121 ppar = 0, 122 psor = 0, 123 pdir = 0, 124 podr = 0, 125 pdat = 0; 126 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 127 iop_conf_t *eiopc = iopc + 32; 128 uint msk = 1; 129 130 /* 131 * NOTE: 132 * index 0 refers to pin 31, 133 * index 31 refers to pin 0 134 */ 135 while (iopc < eiopc) { 136 if (iopc->conf) { 137 pmsk |= msk; 138 if (iopc->ppar) 139 ppar |= msk; 140 if (iopc->psor) 141 psor |= msk; 142 if (iopc->pdir) 143 pdir |= msk; 144 if (iopc->podr) 145 podr |= msk; 146 if (iopc->pdat) 147 pdat |= msk; 148 } 149 150 msk <<= 1; 151 iopc++; 152 } 153 154 if (pmsk != 0) { 155 volatile ioport_t *iop = ioport_addr (cpm, portnum); 156 uint tpmsk = ~pmsk; 157 158 /* 159 * the (somewhat confused) paragraph at the 160 * bottom of page 35-5 warns that there might 161 * be "unknown behaviour" when programming 162 * PSORx and PDIRx, if PPARx = 1, so I 163 * decided this meant I had to disable the 164 * dedicated function first, and enable it 165 * last. 166 */ 167 iop->ppar &= tpmsk; 168 iop->psor = (iop->psor & tpmsk) | psor; 169 iop->podr = (iop->podr & tpmsk) | podr; 170 iop->pdat = (iop->pdat & tpmsk) | pdat; 171 iop->pdir = (iop->pdir & tpmsk) | pdir; 172 iop->ppar |= ppar; 173 } 174 } 175 } 176 #endif 177 178 #ifdef CONFIG_SYS_FSL_CPC 179 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) 180 static void disable_cpc_sram(void) 181 { 182 int i; 183 184 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 185 186 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 187 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 188 /* find and disable LAW of SRAM */ 189 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 190 191 if (law.index == -1) { 192 printf("\nFatal error happened\n"); 193 return; 194 } 195 disable_law(law.index); 196 197 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 198 out_be32(&cpc->cpccsr0, 0); 199 out_be32(&cpc->cpcsrcr0, 0); 200 } 201 } 202 } 203 #endif 204 205 static void enable_cpc(void) 206 { 207 int i; 208 u32 size = 0; 209 210 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 211 212 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 213 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 214 size += CPC_CFG0_SZ_K(cpccfg0); 215 216 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 217 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 218 #endif 219 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 220 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 221 #endif 222 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 223 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 224 #endif 225 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 226 if (has_erratum_a006379()) { 227 setbits_be32(&cpc->cpchdbcr0, 228 CPC_HDBCR0_SPLRU_LEVEL_EN); 229 } 230 #endif 231 232 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 233 /* Read back to sync write */ 234 in_be32(&cpc->cpccsr0); 235 236 } 237 238 puts("Corenet Platform Cache: "); 239 print_size(size * 1024, " enabled\n"); 240 } 241 242 static void invalidate_cpc(void) 243 { 244 int i; 245 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 246 247 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 248 /* skip CPC when it used as all SRAM */ 249 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 250 continue; 251 /* Flash invalidate the CPC and clear all the locks */ 252 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 253 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 254 ; 255 } 256 } 257 #else 258 #define enable_cpc() 259 #define invalidate_cpc() 260 #endif /* CONFIG_SYS_FSL_CPC */ 261 262 /* 263 * Breathe some life into the CPU... 264 * 265 * Set up the memory map 266 * initialize a bunch of registers 267 */ 268 269 #ifdef CONFIG_FSL_CORENET 270 static void corenet_tb_init(void) 271 { 272 volatile ccsr_rcpm_t *rcpm = 273 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 274 volatile ccsr_pic_t *pic = 275 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 276 u32 whoami = in_be32(&pic->whoami); 277 278 /* Enable the timebase register for this core */ 279 out_be32(&rcpm->ctbenrl, (1 << whoami)); 280 } 281 #endif 282 283 void cpu_init_f (void) 284 { 285 extern void m8560_cpm_reset (void); 286 #ifdef CONFIG_SYS_DCSRBAR_PHYS 287 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 288 #endif 289 #if defined(CONFIG_SECURE_BOOT) 290 struct law_entry law; 291 #endif 292 #ifdef CONFIG_MPC8548 293 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 294 uint svr = get_svr(); 295 296 /* 297 * CPU2 errata workaround: A core hang possible while executing 298 * a msync instruction and a snoopable transaction from an I/O 299 * master tagged to make quick forward progress is present. 300 * Fixed in silicon rev 2.1. 301 */ 302 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 303 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 304 #endif 305 306 disable_tlb(14); 307 disable_tlb(15); 308 309 #if defined(CONFIG_SECURE_BOOT) 310 /* Disable the LAW created for NOR flash by the PBI commands */ 311 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 312 if (law.index != -1) 313 disable_law(law.index); 314 315 #if defined(CONFIG_SYS_CPC_REINIT_F) 316 disable_cpc_sram(); 317 #endif 318 #endif 319 320 #ifdef CONFIG_CPM2 321 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 322 #endif 323 324 init_early_memctl_regs(); 325 326 #if defined(CONFIG_CPM2) 327 m8560_cpm_reset(); 328 #endif 329 330 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 331 /* Config QE ioports */ 332 config_qe_ioports(); 333 #endif 334 335 #if defined(CONFIG_FSL_DMA) 336 dma_init(); 337 #endif 338 #ifdef CONFIG_FSL_CORENET 339 corenet_tb_init(); 340 #endif 341 init_used_tlb_cams(); 342 343 /* Invalidate the CPC before DDR gets enabled */ 344 invalidate_cpc(); 345 346 #ifdef CONFIG_SYS_DCSRBAR_PHYS 347 /* set DCSRCR so that DCSR space is 1G */ 348 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 349 in_be32(&gur->dcsrcr); 350 #endif 351 352 } 353 354 /* Implement a dummy function for those platforms w/o SERDES */ 355 static void __fsl_serdes__init(void) 356 { 357 return ; 358 } 359 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 360 361 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 362 int enable_cluster_l2(void) 363 { 364 int i = 0; 365 u32 cluster; 366 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 367 struct ccsr_cluster_l2 __iomem *l2cache; 368 369 cluster = in_be32(&gur->tp_cluster[i].lower); 370 if (cluster & TP_CLUSTER_EOC) 371 return 0; 372 373 /* The first cache has already been set up, so skip it */ 374 i++; 375 376 /* Look through the remaining clusters, and set up their caches */ 377 do { 378 int j, cluster_valid = 0; 379 380 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 381 382 cluster = in_be32(&gur->tp_cluster[i].lower); 383 384 /* check that at least one core/accel is enabled in cluster */ 385 for (j = 0; j < 4; j++) { 386 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 387 u32 type = in_be32(&gur->tp_ityp[idx]); 388 389 if (type & TP_ITYP_AV) 390 cluster_valid = 1; 391 } 392 393 if (cluster_valid) { 394 /* set stash ID to (cluster) * 2 + 32 + 1 */ 395 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 396 397 printf("enable l2 for cluster %d %p\n", i, l2cache); 398 399 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 400 while ((in_be32(&l2cache->l2csr0) 401 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 402 ; 403 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 404 } 405 i++; 406 } while (!(cluster & TP_CLUSTER_EOC)); 407 408 return 0; 409 } 410 #endif 411 412 /* 413 * Initialize L2 as cache. 414 * 415 * The newer 8548, etc, parts have twice as much cache, but 416 * use the same bit-encoding as the older 8555, etc, parts. 417 * 418 */ 419 int cpu_init_r(void) 420 { 421 __maybe_unused u32 svr = get_svr(); 422 #ifdef CONFIG_SYS_LBC_LCRR 423 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 424 #endif 425 #ifdef CONFIG_L2_CACHE 426 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 427 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 428 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 429 #endif 430 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 431 extern int spin_table_compat; 432 const char *spin; 433 #endif 434 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 435 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 436 #endif 437 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 438 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 439 /* 440 * CPU22 and NMG_CPU_A011 share the same workaround. 441 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 442 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 443 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 444 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 445 * be disabled by hwconfig with syntax: 446 * 447 * fsl_cpu_a011:disable 448 */ 449 extern int enable_cpu_a011_workaround; 450 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 451 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 452 #else 453 char buffer[HWCONFIG_BUFFER_SIZE]; 454 char *buf = NULL; 455 int n, res; 456 457 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 458 if (n > 0) 459 buf = buffer; 460 461 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 462 if (res > 0) 463 enable_cpu_a011_workaround = 0; 464 else { 465 if (n >= HWCONFIG_BUFFER_SIZE) { 466 printf("fsl_cpu_a011 was not found. hwconfig variable " 467 "may be too long\n"); 468 } 469 enable_cpu_a011_workaround = 470 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 471 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 472 } 473 #endif 474 if (enable_cpu_a011_workaround) { 475 flush_dcache(); 476 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 477 sync(); 478 } 479 #endif 480 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 481 /* 482 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 483 * in write shadow mode. Checking DCWS before setting SPR 976. 484 */ 485 if (mfspr(L1CSR2) & L1CSR2_DCWS) 486 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 487 #endif 488 489 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 490 spin = getenv("spin_table_compat"); 491 if (spin && (*spin == 'n')) 492 spin_table_compat = 0; 493 else 494 spin_table_compat = 1; 495 #endif 496 497 puts ("L2: "); 498 499 #if defined(CONFIG_L2_CACHE) 500 volatile uint cache_ctl; 501 uint ver; 502 u32 l2siz_field; 503 504 ver = SVR_SOC_VER(svr); 505 506 asm("msync;isync"); 507 cache_ctl = l2cache->l2ctl; 508 509 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 510 if (cache_ctl & MPC85xx_L2CTL_L2E) { 511 /* Clear L2 SRAM memory-mapped base address */ 512 out_be32(&l2cache->l2srbar0, 0x0); 513 out_be32(&l2cache->l2srbar1, 0x0); 514 515 /* set MBECCDIS=0, SBECCDIS=0 */ 516 clrbits_be32(&l2cache->l2errdis, 517 (MPC85xx_L2ERRDIS_MBECC | 518 MPC85xx_L2ERRDIS_SBECC)); 519 520 /* set L2E=0, L2SRAM=0 */ 521 clrbits_be32(&l2cache->l2ctl, 522 (MPC85xx_L2CTL_L2E | 523 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 524 } 525 #endif 526 527 l2siz_field = (cache_ctl >> 28) & 0x3; 528 529 switch (l2siz_field) { 530 case 0x0: 531 printf(" unknown size (0x%08x)\n", cache_ctl); 532 return -1; 533 break; 534 case 0x1: 535 if (ver == SVR_8540 || ver == SVR_8560 || 536 ver == SVR_8541 || ver == SVR_8555) { 537 puts("128 KiB "); 538 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 539 cache_ctl = 0xc4000000; 540 } else { 541 puts("256 KiB "); 542 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 543 } 544 break; 545 case 0x2: 546 if (ver == SVR_8540 || ver == SVR_8560 || 547 ver == SVR_8541 || ver == SVR_8555) { 548 puts("256 KiB "); 549 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 550 cache_ctl = 0xc8000000; 551 } else { 552 puts("512 KiB "); 553 /* set L2E=1, L2I=1, & L2SRAM=0 */ 554 cache_ctl = 0xc0000000; 555 } 556 break; 557 case 0x3: 558 puts("1024 KiB "); 559 /* set L2E=1, L2I=1, & L2SRAM=0 */ 560 cache_ctl = 0xc0000000; 561 break; 562 } 563 564 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 565 puts("already enabled"); 566 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 567 u32 l2srbar = l2cache->l2srbar0; 568 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 569 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 570 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 571 l2cache->l2srbar0 = l2srbar; 572 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 573 } 574 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 575 puts("\n"); 576 } else { 577 asm("msync;isync"); 578 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 579 asm("msync;isync"); 580 puts("enabled\n"); 581 } 582 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 583 if (SVR_SOC_VER(svr) == SVR_P2040) { 584 puts("N/A\n"); 585 goto skip_l2; 586 } 587 588 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 589 590 /* invalidate the L2 cache */ 591 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 592 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 593 ; 594 595 #ifdef CONFIG_SYS_CACHE_STASHING 596 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 597 mtspr(SPRN_L2CSR1, (32 + 1)); 598 #endif 599 600 /* enable the cache */ 601 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 602 603 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 604 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 605 ; 606 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 607 } 608 609 skip_l2: 610 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 611 if (l2cache->l2csr0 & L2CSR0_L2E) 612 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 613 " enabled\n"); 614 615 enable_cluster_l2(); 616 #else 617 puts("disabled\n"); 618 #endif 619 620 #if defined(CONFIG_RAMBOOT_PBL) 621 disable_cpc_sram(); 622 #endif 623 enable_cpc(); 624 625 #ifndef CONFIG_SYS_FSL_NO_SERDES 626 /* needs to be in ram since code uses global static vars */ 627 fsl_serdes_init(); 628 #endif 629 630 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 631 #define MCFGR_AXIPIPE 0x000000f0 632 if (IS_SVR_REV(svr, 1, 0)) 633 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); 634 #endif 635 636 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 637 if (IS_SVR_REV(svr, 1, 0)) { 638 int i; 639 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 640 641 for (i = 0; i < 12; i++) { 642 p += i + (i > 5 ? 11 : 0); 643 out_be32(p, 0x2); 644 } 645 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 646 out_be32(p, 0x34); 647 } 648 #endif 649 650 #ifdef CONFIG_SYS_SRIO 651 srio_init(); 652 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 653 char *s = getenv("bootmaster"); 654 if (s) { 655 if (!strcmp(s, "SRIO1")) { 656 srio_boot_master(1); 657 srio_boot_master_release_slave(1); 658 } 659 if (!strcmp(s, "SRIO2")) { 660 srio_boot_master(2); 661 srio_boot_master_release_slave(2); 662 } 663 } 664 #endif 665 #endif 666 667 #if defined(CONFIG_MP) 668 setup_mp(); 669 #endif 670 671 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 672 { 673 if (SVR_MAJ(svr) < 3) { 674 void *p; 675 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 676 setbits_be32(p, 1 << (31 - 14)); 677 } 678 } 679 #endif 680 681 #ifdef CONFIG_SYS_LBC_LCRR 682 /* 683 * Modify the CLKDIV field of LCRR register to improve the writing 684 * speed for NOR flash. 685 */ 686 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 687 __raw_readl(&lbc->lcrr); 688 isync(); 689 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 690 udelay(100); 691 #endif 692 #endif 693 694 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 695 { 696 struct ccsr_usb_phy __iomem *usb_phy1 = 697 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 698 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 699 if (has_erratum_a006261()) 700 fsl_erratum_a006261_workaround(usb_phy1); 701 #endif 702 out_be32(&usb_phy1->usb_enable_override, 703 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 704 } 705 #endif 706 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 707 { 708 struct ccsr_usb_phy __iomem *usb_phy2 = 709 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 710 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 711 if (has_erratum_a006261()) 712 fsl_erratum_a006261_workaround(usb_phy2); 713 #endif 714 out_be32(&usb_phy2->usb_enable_override, 715 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 716 } 717 #endif 718 719 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 720 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 721 * multi-bit ECC errors which has impact on performance, so software 722 * should disable all ECC reporting from USB1 and USB2. 723 */ 724 if (IS_SVR_REV(get_svr(), 1, 0)) { 725 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 726 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 727 setbits_be32(&dcfg->ecccr1, 728 (DCSR_DCFG_ECC_DISABLE_USB1 | 729 DCSR_DCFG_ECC_DISABLE_USB2)); 730 } 731 #endif 732 733 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 734 struct ccsr_usb_phy __iomem *usb_phy = 735 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 736 setbits_be32(&usb_phy->pllprg[1], 737 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 738 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 739 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 740 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 741 setbits_be32(&usb_phy->port1.ctrl, 742 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 743 setbits_be32(&usb_phy->port1.drvvbuscfg, 744 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 745 setbits_be32(&usb_phy->port1.pwrfltcfg, 746 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 747 setbits_be32(&usb_phy->port2.ctrl, 748 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 749 setbits_be32(&usb_phy->port2.drvvbuscfg, 750 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 751 setbits_be32(&usb_phy->port2.pwrfltcfg, 752 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 753 754 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 755 if (has_erratum_a006261()) 756 fsl_erratum_a006261_workaround(usb_phy); 757 #endif 758 759 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ 760 761 #ifdef CONFIG_FMAN_ENET 762 fman_enet_init(); 763 #endif 764 765 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 766 /* 767 * For P1022/1013 Rev1.0 silicon, after power on SATA host 768 * controller is configured in legacy mode instead of the 769 * expected enterprise mode. Software needs to clear bit[28] 770 * of HControl register to change to enterprise mode from 771 * legacy mode. We assume that the controller is offline. 772 */ 773 if (IS_SVR_REV(svr, 1, 0) && 774 ((SVR_SOC_VER(svr) == SVR_P1022) || 775 (SVR_SOC_VER(svr) == SVR_P1013))) { 776 fsl_sata_reg_t *reg; 777 778 /* first SATA controller */ 779 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 780 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 781 782 /* second SATA controller */ 783 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 784 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 785 } 786 #endif 787 788 789 return 0; 790 } 791 792 void arch_preboot_os(void) 793 { 794 u32 msr; 795 796 /* 797 * We are changing interrupt offsets and are about to boot the OS so 798 * we need to make sure we disable all async interrupts. EE is already 799 * disabled by the time we get called. 800 */ 801 msr = mfmsr(); 802 msr &= ~(MSR_ME|MSR_CE); 803 mtmsr(msr); 804 } 805 806 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 807 int sata_initialize(void) 808 { 809 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 810 return __sata_initialize(); 811 812 return 1; 813 } 814 #endif 815 816 void cpu_secondary_init_r(void) 817 { 818 #ifdef CONFIG_U_QE 819 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ 820 #elif defined CONFIG_QE 821 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 822 #endif 823 824 #ifdef CONFIG_QE 825 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 826 int ret; 827 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; 828 829 /* load QE firmware from NAND flash to DDR first */ 830 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, 831 &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); 832 833 if (ret && ret == -EUCLEAN) { 834 printf ("NAND read for QE firmware at offset %x failed %d\n", 835 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); 836 } 837 #endif 838 qe_init(qe_base); 839 qe_reset(); 840 #endif 841 } 842