| 238c00d9 | 29-May-2022 |
Qiqi Zhang <eddy.zhang@rock-chips.com> |
clk: rockchip: rk3036: add support to set and get pwm clock
Change-Id: I896c97bac5fa1e5aa36545fe5dd1a2c73e623baa Signed-off-by: Qiqi Zhang <eddy.zhang@rock-chips.com> |
| 23b6510b | 20-May-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: optimized Pll automatic calculation
Change-Id: I920fbe21caa5fe8e198985564b474f85028e16f6 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 056cae5c | 13-Apr-2022 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3588: change cpul clock source to pvtpll
Change-Id: I4ab6d15c05b4cb805b60125cb5bb7e7d2e65d6e5 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> |
| 2a12b75e | 11-Apr-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: add wdt clk
Change-Id: I74634dc216b09400c1abe3fbf42106accf9f0108 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 3a7297c2 | 21-Apr-2022 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rk3588: Init the PPLL to 1.1G
The pcie2 combophy clk output will have better quality in this setting.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Change-Id: I9e312123a51d7f34c6c22780
clk: rk3588: Init the PPLL to 1.1G
The pcie2 combophy clk output will have better quality in this setting.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Change-Id: I9e312123a51d7f34c6c22780148f63d14c147442
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| 2909d91b | 20-Apr-2022 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rk3588: Add 1.1G parameter for PLL
PPLL may need to use 1.1G Hz.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Change-Id: I81a86e0fe47c88a0aefced6502723a8469ec59e0 |
| b81ef8b2 | 15-Apr-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: add dclk_decom
Change-Id: Ied47331ddb33fc73491875743667f1e4afcb8eb2 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 32914815 | 26-Mar-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: add grf clk
add grf clk for emmc\sdio\sdmmc sample and drv.
Change-Id: I35c1c7aa0387e3d62fed37264a23a230e45e7194 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| b6f99bec | 24-Mar-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: fix up saradc setting error
Change-Id: Ica5b054a76b68ff29bec24ed04ca30475d3a2303 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 75bf999a | 22-Mar-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: add core div setting
fix kernel clk summary: pll_apll 1 1 0 816000000 apll 1 1 0 816
clk: rockchip: rv1106: add core div setting
fix kernel clk summary: pll_apll 1 1 0 816000000 apll 1 1 0 816000000 armclk 1 1 0 408000000
Change-Id: I4fc0a20d36c6768b4dd26f61ef74c28d2b0c97ff Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| 0d5d7ee2 | 21-Mar-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: fix dpll get rate error
support dpll get rate. init apll to 816M.
Change-Id: I654985cdbfc05293a572c71569fefe92a6906570 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| f5b1a4f2 | 17-Mar-2022 |
Jianqun Xu <jay.xu@rock-chips.com> |
clk: rockchip: px30 set i2s1 mclk out rate to 11289600 Hz
The px30 i2s1 mclk default to source from gpll, it may outputs 100 MHz when the gpll rate up to 1200MHz. Some slave codec may fail to work a
clk: rockchip: px30 set i2s1 mclk out rate to 11289600 Hz
The px30 i2s1 mclk default to source from gpll, it may outputs 100 MHz when the gpll rate up to 1200MHz. Some slave codec may fail to work at the high frequency.
This patch will set the i2s1 mclk source from xin_osc_half before gpll rate up, and then set to 11289600 Hz after gpll rate up.
Change-Id: I2a7641ed7c0db794e50aaacbbc6bb361a8b5db72 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
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| a8b73cd2 | 16-Mar-2022 |
Damon Ding <damon.ding@rock-chips.com> |
clk: rockchip: rk3588: fix up clk_pwm1 setting error
Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Change-Id: I391357118f8f0c5fd55703ae9aaa27d64d63b173 |
| 89cc3f4d | 10-Aug-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: px30: add otp clk and support px30s
Change-Id: I4e16a4e28a25ce3897a368a35da560faf8264640 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 7d793375 | 02-Mar-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: support rockchip image tiny
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Change-Id: I59bc654ea6ebd3a9c7e847b99433c713b850ed6e |
| ec073f31 | 07-Mar-2022 |
Jason Zhu <jason.zhu@rock-chips.com> |
clk: rockchip: px30: support crypto clock in spl
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Change-Id: I68498fc96d244eb9eafda1baa2ca74ef72d27727 |
| a5a5ddb9 | 18-Jan-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: Add clock controller for the RV1106
Add the clock tree definition for the new RV1106 SoC.
Change-Id: Ifc9778851608337fda121297cc0d1200706cf72b Signed-off-by: Elaine Zhang <zhangqing@
clk: rockchip: Add clock controller for the RV1106
Add the clock tree definition for the new RV1106 SoC.
Change-Id: Ifc9778851608337fda121297cc0d1200706cf72b Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| b6d6b016 | 24-Feb-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
clk: rockchip: rk3588: support setting dp aux channel clk
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com> Change-Id: I65954d0805ce51c042dd5ca469781fb55ab1bccc |
| c22f6846 | 23-Feb-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: set b0pll b1pll to 1200M in SPL
Change-Id: Idc47b57e940da7d9c4deeceba004bc5fc8d6c2ad Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 02b00901 | 14-Feb-2022 |
Algea Cao <algea.cao@rock-chips.com> |
clk: rockchip: rk3588: Identify the dclk's parent by device name
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: I6cb07de419eb0702a2b4445a059f96a44b7856c8 |
| d6a0e942 | 14-Feb-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: fix up dclk_vop3 setting error
Change-Id: I345a254f9adaf44d6dcd2bf37b4f429676643e44 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| da48e024 | 22-Jan-2022 |
Algea Cao <algea.cao@rock-chips.com> |
clk: rockchip: rk3588: Support hdmiphy pll
Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: I4fa787ed2b6057579985ab8469adef888eee1ee7 |
| 477e465d | 21-Jan-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: support aclk_vop to 850M
Change-Id: I1a42434e63e6fb6d55dc80827304e2c78ef3dcf1 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 40801113 | 15-Dec-2021 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3588: Use scmi clk for cpub
Change-Id: Iac761088bd65d14f906fb0fe212d307b00f5d6c7 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> |
| 1ca40e22 | 30-Dec-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3288: add clk_test setting
Change-Id: I3c3696d96e83cfad88ad417b322f65f079f1d702 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |