| 5c6e0812 | 17-Jun-2025 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3576: fix cci\big\litcore init
If core select pvtpll in ddr,not need init in spl.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Change-Id: I653ad0836eb6c05591c2105705c2ee3
clk: rockchip: rk3576: fix cci\big\litcore init
If core select pvtpll in ddr,not need init in spl.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Change-Id: I653ad0836eb6c05591c2105705c2ee3038feeefb
show more ...
|
| 5683539d | 17-Jun-2025 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1126b: fix clk_cpll_div10 default div
modify div 10 to div 12.
Change-Id: I866b5f4f8b9bc8c1369ea7407b404ca733ca185e Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 56591f59 | 27-May-2025 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1126b: add mac clks
Change-Id: Ic46307f085fab250197381133a2e3dd569dd274f Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 3602da55 | 22-May-2025 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1126b: fix clk enable/disable return val
Fix: 1be17b4c7804 ("clk: rockchip: rv1126b: add rkce clk enable/disable in spl")
Change-Id: I335050aa9386e0e526d6aec9ebfb05179cd4b5f6 Signe
clk: rockchip: rv1126b: fix clk enable/disable return val
Fix: 1be17b4c7804 ("clk: rockchip: rv1126b: add rkce clk enable/disable in spl")
Change-Id: I335050aa9386e0e526d6aec9ebfb05179cd4b5f6 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|
| 41bbe61e | 15-Apr-2025 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1126b: fix return err for rv1126b_clk_set_rate
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Change-Id: Ib60d502bda640d00b4e8e9ec5aa20f8ca107777a |
| 1be17b4c | 11-Apr-2025 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1126b: add rkce clk enable/disable in spl
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Change-Id: Ia147f080eca3caa7fb8ba6bf3c9c533f919e9746 |
| 4a251cba | 09-Apr-2025 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1126b: set clk_pka_rkce to 198M in spl
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Change-Id: Iabb63ac48d3f815be0522847318530fd5c05fb86 |
| d2c37103 | 31-Mar-2025 |
Damon Ding <damon.ding@rock-chips.com> |
clk: rockchip: rk3576: expand pll rate table to support 152.6M vop dclk rate
Change-Id: I7878a38e83c3da436b0dd4f4485c71609e51980a Signed-off-by: Damon Ding <damon.ding@rock-chips.com> |
| 26b67b4b | 31-Mar-2025 |
Damon Ding <damon.ding@rock-chips.com> |
clk: rockchip: rk3576: set RK3576_VOP_PLL_LIMIT_FREQ to 594M
Sync the pll frequency limit with Kernel in order to avoid the inconsistency of frequency division between Uboot and Kernel when the pare
clk: rockchip: rk3576: set RK3576_VOP_PLL_LIMIT_FREQ to 594M
Sync the pll frequency limit with Kernel in order to avoid the inconsistency of frequency division between Uboot and Kernel when the parent of vop dclk is VPLL.
Change-Id: I667c3ebce04fb772bce8c17b88ff7203b308b755 Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
show more ...
|
| d744c1e3 | 28-Mar-2025 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1126b: add dclk_vop set/get rate
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Change-Id: Ibd9afe9b29ced64ccb25d2735c8ac10dc1568e29 |
| b991d4b5 | 13-Mar-2025 |
Xuhui Lin <xuhui.lin@rock-chips.com> |
clk: rockchip: Add rv1126b clock driver
Add basic clock for rv1126b which including cpu, mmc, i2c, pwm ...clocks init.
Change-Id: I47ef41d24cd0149aade5defd95446d2b38de3b0c Signed-off-by: Elaine Zha
clk: rockchip: Add rv1126b clock driver
Add basic clock for rv1126b which including cpu, mmc, i2c, pwm ...clocks init.
Change-Id: I47ef41d24cd0149aade5defd95446d2b38de3b0c Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
show more ...
|
| 826d54fb | 24-Dec-2024 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3506: Fix CLK_MAC_OUT
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Change-Id: I223d6ea513c3d97a496838693ba108ff481ad240 |
| f8d37df5 | 11-Oct-2024 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3506: Change core src parent from v1pll to gpll
The v1pll may be disabled in kernel and the gpll is always on.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Change-Id: I0
clk: rockchip: rk3506: Change core src parent from v1pll to gpll
The v1pll may be disabled in kernel and the gpll is always on.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Change-Id: I06dc90709563f7f5e7bc3b6837fc430ae27c1b25
show more ...
|
| 2ecab49f | 26-Aug-2024 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3506: Init clk pka crypto
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Change-Id: I8876ee37827c388e821159d0a41faf2e83326216 |
| ee62ba3d | 01-Aug-2024 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: add 1150M for pll table
Change-Id: I0592228084cd4ad223333413c5e132169f205d82 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 71cb44d0 | 30-Jul-2024 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
clk: rk3588: Init the PPLL to 1.1G by default
The initialization frequency of PPLL needs to be consistent with the kernel to avoid modifying PPLL when loading kernel DTB, which may cause abnormal re
clk: rk3588: Init the PPLL to 1.1G by default
The initialization frequency of PPLL needs to be consistent with the kernel to avoid modifying PPLL when loading kernel DTB, which may cause abnormal reference clock of SATA.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: Icc7bdaf7aa78bde645dc81e3b709a78dd02a552c
show more ...
|
| 5de46d87 | 26-Jul-2024 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3506: Add support for pvtpll
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Change-Id: Ib2cceedd338b723892c8c9451b77ced41f4970f5 |
| cdb92760 | 25-Jul-2024 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3576: add ref_clkout_pll
Change-Id: Id120fafec101568fab94929934667e7bef8c1a09 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| e434c7b0 | 22-Jul-2024 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3506: Add support for mac
Change-Id: I65d586d908396b2dc92f2c6288b29e6fdbc66715 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> |
| 5b7480cd | 04-Jul-2023 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: Add rk3506 clock driver
Add basic clock for rk3506 which including cpu, sdmmc, i2c, pwm ...clocks init.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Change-Id: I5eb862e956
clk: rockchip: Add rk3506 clock driver
Add basic clock for rk3506 which including cpu, sdmmc, i2c, pwm ...clocks init.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Change-Id: I5eb862e95676b14723e12e1d10efaffa51f024cd
show more ...
|
| 76f3cd6a | 15-Apr-2024 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: Add rv1103b clock driver
Add basic clock for rv1103b which including cpu, mmc, i2c, pwm ...clocks init.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Change-Id: I01e2d0ca828
clk: rockchip: Add rv1103b clock driver
Add basic clock for rv1103b which including cpu, mmc, i2c, pwm ...clocks init.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Change-Id: I01e2d0ca828e6a517c4ad0b623ed248dd09e7bd7
show more ...
|
| 0c8b06ef | 29-Apr-2022 |
Joseph Chen <chenjh@rock-chips.com> |
clk: rockchip: rk3308: Don't limit to decrease arm freq
rockchip_wtemp_dvfs.c may decrease the arm freq.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: I49fbf8fc11bc3c3cb954ce0393cb7
clk: rockchip: rk3308: Don't limit to decrease arm freq
rockchip_wtemp_dvfs.c may decrease the arm freq.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: I49fbf8fc11bc3c3cb954ce0393cb72103cf22b51
show more ...
|
| f215d626 | 14-Mar-2024 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3576: fix ebc clk setting rule
Change-Id: I33b63df8d595531df85fdac83f20c7ba104c5008 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 4a69562c | 28-Mar-2024 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3576: add hclk sdmmc/emmc/sdio
Change-Id: I72a7a8ae2b4d0e2e8480f7b2738042069f8b40ab Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 431b7b81 | 19-Mar-2024 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3576: add decom clk setting
Change-Id: I3e0e288938d672b86d80dc91e1b782691695c5fc Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |