common: spl: support enable D-cache for 32-bit platform

- Initial gd->bd->bi_dram[] for arm32.
- Add a configure to enable/disable SPL D-cache.
- Please make sure CONFIG_SPL_SYS_MALLOC_F_LEN is larg

common: spl: support enable D-cache for 32-bit platform

- Initial gd->bd->bi_dram[] for arm32.
- Add a configure to enable/disable SPL D-cache.
- Please make sure CONFIG_SPL_SYS_MALLOC_F_LEN is large
enough for TLB and bd_t buffer while enabling dcache

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I85f2169fe44b44e16edb15a9538df516037e9823

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common: spl: jump next process depend on entry_point_os

The spl can bring up uboot & kernel, and their entry points are diffirent,
so pass their entry points by entry_point_os.

Signed-off-by: Jason

common: spl: jump next process depend on entry_point_os

The spl can bring up uboot & kernel, and their entry points are diffirent,
so pass their entry points by entry_point_os.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I625d135d219cfbfb620ff1e3d0de5278143f4079

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Merge branch 'next-dev' into thunder-boot

common: spl: enable D-cache by default to improve performance

Set CONFIG_SPL_SYS_MALLOC_F_LEN enough to promise the tlb buffer
can be malloc, actually this is a way to compatible all the current
boa

common: spl: enable D-cache by default to improve performance

Set CONFIG_SPL_SYS_MALLOC_F_LEN enough to promise the tlb buffer
can be malloc, actually this is a way to compatible all the current
boards without adding a new configure option.

I-cache has been setup at early assembly code by default.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I7e973299eddc358cd4c15846c5de154050bf9547

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spl: record boot_device into spl_image and call
spl_perform_fixups

On some boards, we want to give the board/architecture-specific code a
chance to look at where the next image has been loaded from

spl: record boot_device into spl_image and call
spl_perform_fixups

On some boards, we want to give the board/architecture-specific code a
chance to look at where the next image has been loaded from and
perform fixups before starting the next image. This is of particular
importance, when we probe multiple devices for bootable payloads and
boot the first one found.

This change adds the following:
- we record the boot_device used into the spl_image structure
- we provide an extension-point for boards/architectures that can
perform late fixups depending on a fully populated spl_image
structure (i.e. we'll know the final boot_device and have info
on the image type and operating system to be booted).

Change-Id: Iebca59a61979bc12eabe743c73dc2279e870e2ff
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>

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common: spl: printf message when jump to ATF

Change-Id: Ibd970ffc3078c3bbe93cbd65698052cd913a31f6
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

common: spl: atf: add bl32/bl33 entry point to struct spl_image_info

This allows other booting device to initial other firmware entry
point, but not only FIT.

Change-Id: I73b08d594079ce0842b68f1c9d

common: spl: atf: add bl32/bl33 entry point to struct spl_image_info

This allows other booting device to initial other firmware entry
point, but not only FIT.

Change-Id: I73b08d594079ce0842b68f1c9d222f58e171b555
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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spl: add relocation support

Some times we want to relocate spl code to dram after dram
initialization or relocate spl code to a high memory to avoid
code overide.

For example on Rockchip armv8 plat

spl: add relocation support

Some times we want to relocate spl code to dram after dram
initialization or relocate spl code to a high memory to avoid
code overide.

For example on Rockchip armv8 platform, we run with boot flow
TPL->SPL->ATF->U-Boot.

TPL run in sram and is responsible for dram initialization.
SPL run from the start address of dram and is responsible for
loading ATF and U-Boot.

The case here is that the ATF load address is from 64KB of dram,
which overlaps with spl code itself.

So we want to relocate spl itself to high memory to aovid this.

Change-Id: Ifcae4444c04fa1208406b51196cf8737277ace90
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

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spl: use different BOARD_INIT MACRO for spl and tpl

SPL and TPL may not always need spl_board_init() at the same time.

Change-Id: I5f26956414f1d2ff3fd2fce11a4d7759de7804fe
Signed-off-by: Kever Yang

spl: use different BOARD_INIT MACRO for spl and tpl

SPL and TPL may not always need spl_board_init() at the same time.

Change-Id: I5f26956414f1d2ff3fd2fce11a4d7759de7804fe
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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spl: add support to booting with OP-TEE

OP-TEE is an open source trusted OS, in armv7, its loading and
running are like this:
loading:
- SPL load both OP-TEE and U-Boot
running:
- SPL run into OP-TE

spl: add support to booting with OP-TEE

OP-TEE is an open source trusted OS, in armv7, its loading and
running are like this:
loading:
- SPL load both OP-TEE and U-Boot
running:
- SPL run into OP-TEE in secure mode;
- OP-TEE run into U-Boot in non-secure mode;

More detail:
https://github.com/OP-TEE/optee_os
and search for 'boot arguments' for detail entry parameter in:
core/arch/arm/kernel/generic_entry_a32.S

Change-Id: I1344a35dd11bd69ca00e9b99909e1eb610648d86
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 32470d8ebee6a9c31a7a6b82704c486ef06cf549)

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spl: atf: introduce spl_invoke_atf and make bl31_entry private

This adds a new interface spl_invoke_atf() that takes a spl_image_info
argument and then derives the necessary parameters for the ATF e

spl: atf: introduce spl_invoke_atf and make bl31_entry private

This adds a new interface spl_invoke_atf() that takes a spl_image_info
argument and then derives the necessary parameters for the ATF entry.
Based on the additional information recorded (into /fit-images) from
the FIT loadables, we can now easily locate the next boot stage.

We now pass a pointer to a FDT as the platform-specific parameter
pointer to ATF (so we don't run into the future headache of every
board/platform defining their own proprietary tag-structure), as
FDT access is already available in ATF.

With the necessary infrastructure in place, we can now update the
support for the ARM Trusted Firmware to dispatch into the
spl_invoke_atf function only if a IH_OS_ARM_TRUSTED_FIRMWARE image is
loaded.

Change-Id: Ia00abe207a0a0fed044fcda2b6e1054225b42901
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 1d3790905d9c089b434c376f2dcc585b6a92bc99)

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UPSTREAM: SPL: fix printing of image name

The maximum length of the name of the image is
obviously not sizeof(), which is just the
length of a pointer, but IH_NMLEN.

fixes: 62cf11c0921a90c6bd62344f

UPSTREAM: SPL: fix printing of image name

The maximum length of the name of the image is
obviously not sizeof(), which is just the
length of a pointer, but IH_NMLEN.

fixes: 62cf11c0921a90c6bd62344f4bc069668e6c698c
("SPL: Limit image name print length")

Change-Id: I948dee1b9a4e1ddfbb122475e2d209cc26dec9d0
Signed-off-by: André Draszik <adraszik@tycoint.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 3fe3839acc4a5d9b1af9b2ab3884b0d3f2e23370)

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UPSTREAM: spl: fix assignment of board info to global data

Commit 15eb1d43bf47 ("spl: reorder the assignment of board info to
global data") intended to move assignment of board info earlier,
into bo

UPSTREAM: spl: fix assignment of board info to global data

Commit 15eb1d43bf47 ("spl: reorder the assignment of board info to
global data") intended to move assignment of board info earlier,
into board_init_r(). However, function preload_console_init() is
called either from spl_board_init() or from board_init_f(). For the
latter case, the board info assignment is much earlier than proposed
board_init_r(). Create a new function to fill gd->bd and call this
function when needed.

Change-Id: I3e8da19121f5b82f116b9d051b75acdd777c2475
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Ravi Babu <ravibabu@ti.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit d1fc0a31b5f307c92b7a047d4f90d5ad2e54cdcc)

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UPSTREAM: spl: add newline in debug output

With debug enabled, SPL output following these debug prints is on the
same line and it is hard to read. Fix it.

Change-Id: I6b0983a285f1deb38cac7e0292c9c2

UPSTREAM: spl: add newline in debug output

With debug enabled, SPL output following these debug prints is on the
same line and it is hard to read. Fix it.

Change-Id: I6b0983a285f1deb38cac7e0292c9c286ca6e901b
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 2d2531be861cb7ec25aa7980b1099ca4f5f46d86)

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spl: stash bootstage info before jump to next stage

Since we may jump to next stage like ATF/OP-TEE instead of U-Boot,
we need to stash the bootstage info before it.

Change-Id: I4de48f95291be638cc5

spl: stash bootstage info before jump to next stage

Since we may jump to next stage like ATF/OP-TEE instead of U-Boot,
we need to stash the bootstage info before it.

Change-Id: I4de48f95291be638cc57be25c2bc27f526d9f9f0
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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spl: update bl31_entry() with new name and parameter

Rename the bl31_entry() function with 'spl_' prefix and add one
parameter for bl31 entry address since we can get it from spl_image header.

Chan

spl: update bl31_entry() with new name and parameter

Rename the bl31_entry() function with 'spl_' prefix and add one
parameter for bl31 entry address since we can get it from spl_image header.

Change-Id: I4b6125f1d7138f26c2256ab86f449be4a6f1c4cc
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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spl: add support to booting with OP-TEE

OP-TEE is an open source trusted OS, in armv7, its loading and
running are like this:
loading:
- SPL load both OP-TEE and U-Boot
running:
- SPL run into OP-TE

spl: add support to booting with OP-TEE

OP-TEE is an open source trusted OS, in armv7, its loading and
running are like this:
loading:
- SPL load both OP-TEE and U-Boot
running:
- SPL run into OP-TEE in secure mode;
- OP-TEE run into U-Boot in non-secure mode;

More detail:
https://github.com/OP-TEE/optee_os
and search for 'boot arguments' for detail entry parameter in:
core/arch/arm/kernel/generic_entry_a32.S

Change-Id: I1344a35dd11bd69ca00e9b99909e1eb610648d86
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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Merge git://git.denx.de/u-boot-imx

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
configs/imx6qdl_icore_mmc_defconfig
configs/imx6qdl_icore_rqs_defconfig

spl: do not repeat timer init on i.MX6

The GPT timer was already initialised in board_init_f() as
it is needed in dram init. Do not repeat timer init in
board_init_r().

Signed-off-by: Anatolij Gust

spl: do not repeat timer init on i.MX6

The GPT timer was already initialised in board_init_f() as
it is needed in dram init. Do not repeat timer init in
board_init_r().

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>

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Merge branch 'master' of git://git.denx.de/u-boot-rockchip

spl: dm: use CONFIG_IS_ENABLED to test for the DM option

Even though there's now a TPL_DM configuration option, the spl logic
still checks for SPL_DM and thus does not pick up the proper config
opti

spl: dm: use CONFIG_IS_ENABLED to test for the DM option

Even though there's now a TPL_DM configuration option, the spl logic
still checks for SPL_DM and thus does not pick up the proper config
option.

This introduces the use of CONFIG_IS_ENABLED(DM) in spl.c to always
pick up the desired configuration option instead of having a
hard-coded check for the SPL variant.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

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spl: use TPL_SYS_MALLOC_F_LEN for TPL

The (upstream) changes to break up SYS_MALLOC_F_LEN for the full
U-Boot and the SPL stage, break TPL (if simple malloc is enabled in
TPL).

This adds support fo

spl: use TPL_SYS_MALLOC_F_LEN for TPL

The (upstream) changes to break up SYS_MALLOC_F_LEN for the full
U-Boot and the SPL stage, break TPL (if simple malloc is enabled in
TPL).

This adds support for a TPL-variant of SYS_MALLOC_F_LEN:
- adds TPL_SYS_MALLOC_F_LEN
- rewrites a test for CONFIG_SPL_SYS_MALLOC_F_LEN to access
CONFIG_VAL(SYS_MALLOC_F_LEN)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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spl: make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN

Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before reloc

spl: make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN

Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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spl: armv7m: to keep ARM v7M in thumb mode before booting next image

On ARM v7M, the processor will return to ARM mode when executing blx
instruction with bit 0 of the address == 0. Always set it to

spl: armv7m: to keep ARM v7M in thumb mode before booting next image

On ARM v7M, the processor will return to ARM mode when executing blx
instruction with bit 0 of the address == 0. Always set it to 1 to stay in thumb
mode.

At present, it is applied only for raw U-Boot. This patch moves it to just
before booting next image. This way armv7m will be in thumb mode for any image
like raw or image with header like zImage or standard U-Boot.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>

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bootstage: Support SPL

At present bootstage only supports U-Boot proper. But SPL can also consume
boot time so it is useful to have the record start there.

Add bootstage support to SPL. Also suppor

bootstage: Support SPL

At present bootstage only supports U-Boot proper. But SPL can also consume
boot time so it is useful to have the record start there.

Add bootstage support to SPL. Also support stashing the timing information
when SPL finishes so that it can be picked up and reported by U-Boot
proper. This provides a full boot time record, excluding only the time
taken by the boot ROM.

Signed-off-by: Simon Glass <sjg@chromium.org>

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