arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1Adding new handoff for SDRAM ctrcfg.extratime1 which isrequired for stable LPDDR2 operation. Since the board isusing DDR3, the han
arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1Adding new handoff for SDRAM ctrcfg.extratime1 which isrequired for stable LPDDR2 operation. Since the board isusing DDR3, the handoff is set to default value 0.Signed-off-by: Chin Liang See <clsee@altera.com>Cc: Marek Vasut <marex@denx.de>Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
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arm: socfpga: sockit: Use more relaxed DRAM timingsThe currently present DRAM timings generated from GHRD 14.0 didnot work on SoCkit rev. D because they were too tight. Load theDRAM timings from
arm: socfpga: sockit: Use more relaxed DRAM timingsThe currently present DRAM timings generated from GHRD 14.0 didnot work on SoCkit rev. D because they were too tight. Load theDRAM timings from GHRD 13.0 which are more relaxed and work withSoCkit rev. D.Signed-off-by: Marek Vasut <marex@denx.de>Cc: Dinh Nguyen <dinguyen@opensource.altera.com>Cc: Chin Liang See <clsee@altera.com>
arm: socfpga: Add support for Terasic SoCkit boardAdd support for Terasic SoCkit, which is CycloneV based board.The board can boot either from SD/MMC or QSPI. Ethernet is alsosupported.Signed-o
arm: socfpga: Add support for Terasic SoCkit boardAdd support for Terasic SoCkit, which is CycloneV based board.The board can boot either from SD/MMC or QSPI. Ethernet is alsosupported.Signed-off-by: Marek Vasut <marex@denx.de>