| #
4ddc9812 |
| 29-Oct-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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| #
1c140fd2 |
| 21-Sep-2016 |
Chin Liang See <clsee@altera.com> |
arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, th
arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
show more ...
|
| #
dc557e9a |
| 18-Jun-2016 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
|
| #
edb697cf |
| 03-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
|
| #
569a191a |
| 01-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Add samtec VIN|ING board
Add support for board based on the popular Altera Cyclone V SoC.
This board has the following properties:
- 1 GiB of DRAM
- 1 Gigabit ethernet
- 1 USB gadge
arm: socfpga: Add samtec VIN|ING board
Add support for board based on the popular Altera Cyclone V SoC.
This board has the following properties:
- 1 GiB of DRAM
- 1 Gigabit ethernet
- 1 USB gadget port
- 1 USB host port with an on-board hub
- 2 QSPI NORs connected to the Cadence QSPI core
- Multiple I2C EEPROMs and one I2C temperature sensor
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
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V2: Update the defconfig as per Tom's request
show more ...
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