arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1Adding new handoff for SDRAM ctrcfg.extratime1 which isrequired for stable LPDDR2 operation. Since the board isusing DDR3, th
arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1Adding new handoff for SDRAM ctrcfg.extratime1 which isrequired for stable LPDDR2 operation. Since the board isusing DDR3, the handoff is set to default value 0.Signed-off-by: Chin Liang See <clsee@altera.com>Cc: Marek Vasut <marex@denx.de>Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
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arm: socfpga: Add samtec VIN|ING boardAdd support for board based on the popular Altera Cyclone V SoC.This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadge
arm: socfpga: Add samtec VIN|ING boardAdd support for board based on the popular Altera Cyclone V SoC.This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensorSigned-off-by: Marek Vasut <marex@denx.de>Cc: Dinh Nguyen <dinguyen@opensource.altera.com>Cc: Chin Liang See <clsee@altera.com>---V2: Update the defconfig as per Tom's request