| #
dc557e9a |
| 18-Jun-2016 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
|
| #
c41c649c |
| 04-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
|
| #
e04f9d0c |
| 04-May-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
board/freescale: Update ddr clk_adjust
This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.
Signed-off-
board/freescale: Update ddr clk_adjust
This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| #
272a1acf |
| 08-Dec-2014 |
Tom Rini <trini@ti.com> |
Merge git://git.denx.de/u-boot-mpc85xx
|
| #
ed9e4e42 |
| 27-Oct-2014 |
York Sun <yorksun@freescale.com> |
mpc85xx/t208xqds: Adjust DDR timing parameters
Adjust timing for dual-rank UDIMM, verified on M3CQ-8GHS3C0E for speed of
1066, 1333, 1600, 1866MT/s. The 1866 timing is copied to 2133 timing in
case
mpc85xx/t208xqds: Adjust DDR timing parameters
Adjust timing for dual-rank UDIMM, verified on M3CQ-8GHS3C0E for speed of
1066, 1333, 1600, 1866MT/s. The 1866 timing is copied to 2133 timing in
case such DIMM comes available.
Also update single-rank 1866 timing. Enable interactive debugging as well.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
show more ...
|
| #
dab5e346 |
| 16-Jul-2014 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
Conflicts:
boards.cfg
|
| #
ed1d98d8 |
| 25-Jun-2014 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
|
| #
3e1fa221 |
| 05-Jun-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
|
| #
40483e1e |
| 20-May-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
board/t2080qds: some update for ddr
- add support for 2nd DIMM slot.
- make it work with DIMM which is less than 2GB.
Verified with two 2GB UDIMM MT9JSF25672AZ-2G1K1 in two DIMM slots.
Signed-off-
board/t2080qds: some update for ddr
- add support for 2nd DIMM slot.
- make it work with DIMM which is less than 2GB.
Verified with two 2GB UDIMM MT9JSF25672AZ-2G1K1 in two DIMM slots.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
show more ...
|
| #
1ad6364e |
| 05-Mar-2014 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
|
| #
a7e8c15f |
| 25-Feb-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
With this, fixup a trivial build error of get_effective_memsize needing
to be updated in the new board/freescale/p1010rdb/spl.c
Signed-off-
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
With this, fixup a trivial build error of get_effective_memsize needing
to be updated in the new board/freescale/p1010rdb/spl.c
Signed-off-by: Tom Rini <trini@ti.com>
show more ...
|
| #
254887a5 |
| 21-Feb-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/t2081qds: Add T2081 QDS board support
T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.
T2081QDS b
powerpc/t2081qds: Add T2081 QDS board support
T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.
T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
- Two on-board 10M/100M/1G bps RGMII ports
- Two 10Gbps XFI with on-board SFP+ cage
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
- Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
- 8 lanes up to 10.3125GHz
- Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
- 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
- Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
voltage translators
- I2C:
- Four I2C controllers.
- UART:
- Dual 4-pins UART serial ports
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
show more ...
|