| #
6e2941d7 |
| 17-May-2017 |
Simon Glass <sjg@chromium.org> |
common: freescale: Move arch-specific declarations
The declarations should not be in common.h. Move them to the arch-specific headers.
Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup th
common: freescale: Move arch-specific declarations
The declarations should not be in common.h. Move them to the arch-specific headers.
Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com>
show more ...
|
| #
3eace37e |
| 06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: freescale: Rename initdram() to fsl_initdram()
This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring.
Sign
arm: freescale: Rename initdram() to fsl_initdram()
This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring.
Signed-off-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
088454cd |
| 31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop return value from initdram()
At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_d
board_f: Drop return value from initdram()
At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
show more ...
|
| #
52c41180 |
| 31-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Drop board_type parameter from initdram()
It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type
board_f: Drop board_type parameter from initdram()
It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
show more ...
|
| #
ce38ebb6 |
| 16-Mar-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
|
| #
36cc0de0 |
| 06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit a
armv8: layerscape: Rewrite memory reservation
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader.
Signed-off-by: York Sun <york.sun@nxp.com>
show more ...
|
| #
b5178a1f |
| 16-Dec-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
|
| #
90101386 |
| 15-Nov-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
fsl/board/ddr: optimize board-specific cpo for erratum A-009942
Optimize board-specific cpo for erratum A-009942 on b4860qds, ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb, t102xqds, t1
fsl/board/ddr: optimize board-specific cpo for erratum A-009942
Optimize board-specific cpo for erratum A-009942 on b4860qds, ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb, t102xqds, t102xrdb, t1040qds, t104xrdb, t208xqds, t208xrdb, t4qds, t4rdb boards.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| #
66669fcf |
| 19-Jul-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts: arch/arm/cpu/armv8/Makefile arch/arm/lib/bootm-fdt.c
|
| #
e61a7534 |
| 24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data
Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure.
Signed-off-
armv8: Move secure_ram variable out of generic global data
Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure.
Signed-off-by: York Sun <york.sun@nxp.com>
show more ...
|
| #
dc557e9a |
| 18-Jun-2016 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
|
| #
fc15b9be |
| 24-May-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
|
| #
074596c0 |
| 07-Apr-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
armv8/ls1043: Add workaround for DDR erratum A-008850
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround
armv8/ls1043: Add workaround for DDR erratum A-008850
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| #
e6e3faa5 |
| 15-Dec-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
|
| #
c107c0c0 |
| 04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables
DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU
armv8: fsl-layerscape: Make DDR non secure in MMU tables
DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area.
Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality.
gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into.
Signed-off-by: York Sun <yorksun@freescale.com>
show more ...
|
| #
e994dddb |
| 23-Nov-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043ardb: Add support for >2GB memory
This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.H
armv8/ls1043ardb: Add support for >2GB memory
This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
show more ...
|
| #
5f5620ab |
| 12-Nov-2015 |
Stefano Babic <sbabic@denx.de> |
Merge git://git.denx.de/u-boot
|
| #
588eec2a |
| 30-Oct-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
|
| #
f3a8e2b7 |
| 26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/ls1043ardb: Add LS1043ARDB board support
LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512
armv8/ls1043ardb: Add LS1043ARDB board support
LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card
Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports
PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot
USB 3.0: two super speed USB 3.0 type A ports
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
show more ...
|