| 1d4c83c2 | 13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Remove legacy timer codes
Now that we have converted all x86 boards to use driver model timer,
remove these legacy timer codes in the tsc driver.
Note this also removes the TSC_CALIBRATIO
x86: tsc: Remove legacy timer codes
Now that we have converted all x86 boards to use driver model timer,
remove these legacy timer codes in the tsc driver.
Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option,
as it is not needed with driver model.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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| 48748595 | 06-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: qemu: Move chipset-specific codes from pci.c to qemu.c
Move chipset-specific codes such as PAM init, PCIe ECAM and MP table
from pci.c to qemu.c, to prepare for DM PCI conversion.
Signed-off-b
x86: qemu: Move chipset-specific codes from pci.c to qemu.c
Move chipset-specific codes such as PAM init, PCIe ECAM and MP table
from pci.c to qemu.c, to prepare for DM PCI conversion.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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| e5ffa4bb | 23-Oct-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: queensbay: Really disable IGD
According to Atom E6xx datasheet, setting VGA Disable (bit17)
of Graphics Controller register (offset 0x50) prevents IGD
(D2:F0) from reporting itself as a VGA dis
x86: queensbay: Really disable IGD
According to Atom E6xx datasheet, setting VGA Disable (bit17)
of Graphics Controller register (offset 0x50) prevents IGD
(D2:F0) from reporting itself as a VGA display controller
class in the PCI configuration space, and should also prevent
it from responding to VGA legacy memory range and I/O addresses.
However test result shows that with just VGA Disable bit set and
a PCIe graphics card connected to one of the PCIe controllers on
the E6xx, accessing the VGA legacy space still causes system hang.
After a number of attempts, it turns out besides VGA Disable bit,
the SDVO (D3:F0) device should be disabled to make it work.
To simplify, use the Function Disable register (offset 0xc4)
to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
two devices will be completely disabled (invisible in the PCI
configuration space) unless a system reset is performed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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| 3e45de6e | 18-Oct-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Enable the MRC cache
This works correctly now, so enable it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Dropped malloc() and adjusted commit message:
Signed-off-by: Simon Glass <s
x86: ivybridge: Enable the MRC cache
This works correctly now, so enable it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Dropped malloc() and adjusted commit message:
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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| fd8f4729 | 18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Measure the MRC code execution time
This code takes about 450ms without the MRC cache and about 27ms with the
cache. Add a debug timer so that this time can be displayed.
Signed-off
x86: ivybridge: Measure the MRC code execution time
This code takes about 450ms without the MRC cache and about 27ms with the
cache. Add a debug timer so that this time can be displayed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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| e9b3967c | 18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Fix car_uninit() to correctly set run state
At present a missing $ causes this code to hang when using the MRC cache/
Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-
x86: ivybridge: Fix car_uninit() to correctly set run state
At present a missing $ causes this code to hang when using the MRC cache/
Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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| 60994a02 | 19-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: Init the debug UART if enabled
If the debug UART is enabled, get it ready for use at the earliest possible
opportunity. This is not actually very early, but until we have a stack it
is difficul
x86: Init the debug UART if enabled
If the debug UART is enabled, get it ready for use at the earliest possible
opportunity. This is not actually very early, but until we have a stack it
is difficult to make it work.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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| ef1683d5 | 14-Oct-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Pass correct cpu_index to ap_init()
In sipi_vector.S, cpu_index (passed as %eax) is wrongly overwritten
by the ap_init() function address. Correct it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.c
x86: Pass correct cpu_index to ap_init()
In sipi_vector.S, cpu_index (passed as %eax) is wrongly overwritten
by the ap_init() function address. Correct it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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| 74e56d19 | 12-Oct-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: baytrail: Issue full system reset in reset_cpu()
With MRC cache enabled, when typing 'reset' in the U-Boot shell,
BayTrail FSP initialization hangs at "Configuring Memory Start":
Setting Boo
x86: baytrail: Issue full system reset in reset_cpu()
With MRC cache enabled, when typing 'reset' in the U-Boot shell,
BayTrail FSP initialization hangs at "Configuring Memory Start":
Setting BootMode to 0
Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
About to call MrcInit();
BayleyBay Platform Type
CurrentMrcData.BootMode = 4
Taking Fastboot path!
Configuring Memory Start...
Changing reset_cpu() to do a full system reset fixes this issue.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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| 4b9f6a66 | 12-Oct-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Use struct mrc_region to describe a mrc region
Currently struct fmap_entry is used to describe a mrc region.
However this structure contains some other fields that are not
related to mrc cache
x86: Use struct mrc_region to describe a mrc region
Currently struct fmap_entry is used to describe a mrc region.
However this structure contains some other fields that are not
related to mrc cache and causes confusion. Besides, it does not
include a base address field to store SPI flash's base address.
Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to
calculate the SPI flash base address, which unfortunately is
not 100% correct as CONFIG_ROM_SIZE may not match the whole
SPI flash size.
Define a new struct mrc_region and use it instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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| 42913a1c | 12-Oct-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Use APIs provided in the mrccache lib
Remove the call to custom mrc cache APIs, and use the ones
provided in the mrccache lib.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by:
x86: ivybridge: Use APIs provided in the mrccache lib
Remove the call to custom mrc cache APIs, and use the ones
provided in the mrccache lib.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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