| 20959471 | 10-Apr-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc: Fix declaration type for I/O functions
Prototype declaration of I/O operation functions are not correct. as both
'extern' and function definition are at same place.
Chage protoype declarat
powerpc: Fix declaration type for I/O functions
Prototype declaration of I/O operation functions are not correct. as both
'extern' and function definition are at same place.
Chage protoype declaration as static.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
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| a16a5ccc | 10-Apr-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc:Fix return type & parameter passed for I/O functions
Return type of in_8, in_be16 and in_le16 should not be'int'. Update it to type
u8/u16/u32.
Although 'unsigned' for in_be32 and in_le32 is
powerpc:Fix return type & parameter passed for I/O functions
Return type of in_8, in_be16 and in_le16 should not be'int'. Update it to type
u8/u16/u32.
Although 'unsigned' for in_be32 and in_le32 is correct. But to make return type
uniform across the file changed to u32
Similarly, parameter passed to out_8, out_be16, out_le16 ,out_be32 & out_le32
should not be 'int'.Change it to type u8/u16/u32.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
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| 5e23ab0a | 07-May-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Workaround for erratum CPU_A011
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same w
powerpc/mpc85xx: Workaround for erratum CPU_A011
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.
Signed-off-by: York Sun <yorksun@freescale.com>
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| 7b6e8053 | 04-May-2012 |
Timur Tabi <timur@freescale.com> |
lib/powerpc: addrmap_phys_to_virt() should return a pointer
addrmap_phys_to_virt() converts a physical address (phys_addr_t) to a
virtual address, so it should return a pointer instead of an unsigne
lib/powerpc: addrmap_phys_to_virt() should return a pointer
addrmap_phys_to_virt() converts a physical address (phys_addr_t) to a
virtual address, so it should return a pointer instead of an unsigned long.
Its counterpart, addrmap_virt_to_phys(), takes a pointer, so now they're
orthogonal.
The only caller of addrmap_phys_to_virt() converts the return value to
a pointer anyway.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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| 5056c8e0 | 08-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core
powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core at the
right time by SRIO interface.
Master needs to:
1. Set outbound SRIO windows in order to configure slave's registers
for the core's releasing.
2. Check the SRIO port status when release slave core, if no errors,
will implement the process of the slave core's releasing.
Slave needs to:
1. Set all the cores in holdoff by RCW.
2. Be powered on before master's boot.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
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| 5ffa88ec | 08-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Master module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can d
powerpc/corenet_ds: Master module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
For the master module, need to finish these processes:
1. Initialize the SRIO port and address space.
2. Set inbound SRIO windows covered slave's u-boot image stored in
master's NOR flash.
3. Master's u-boot image should be generated specifically by
make xxxx_SRIOBOOT_MASTER_config
4. Master must boot first, and then slave can be powered on.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
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| 3e0529f7 | 21-Nov-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA
controller, so it should be defined in config_mpc85xx.h
powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA
controller, so it should be defined in config_mpc85xx.h instead of the various
board header files. So now CONFIG_FSL_SATA_V2 is always defined on the P1013,
P1022, P2041, P3041, P5010, and P5020. It was already defined for the
P1010 and P1014.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 4108508a | 20-Nov-2011 |
York Sun <yorksun@freescale.com> |
powerpc/85xx: Add workaround for erratum A-003474
Erratum A-003474: Internal DDR calibration circuit is not supported
Impact:
Experience shows no significant benefit to device operation with
auto-c
powerpc/85xx: Add workaround for erratum A-003474
Erratum A-003474: Internal DDR calibration circuit is not supported
Impact:
Experience shows no significant benefit to device operation with
auto-calibration enabled versus it disabled. To ensure consistent timing
results, Freescale recommends this feature be disabled in future customer
products. There should be no impact to parts that are already operating
in the field.
Workaround:
Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
1. Write a value of 0x0000_0015 to the register at offset
CCSRBAR + DDR OFFSET + 0xf30
2. Write a value of 0x2400_0000 to the register at offset
CCSRBAR + DDR OFFSET + 0xf54
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 5c4a3d43 | 31-Oct-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: fix definition of MAS register macros
Some of the MAS register macros do not protect the parameter with
parentheses, which could cause wrong values if the parameter includes
operators.
powerpc/85xx: fix definition of MAS register macros
Some of the MAS register macros do not protect the parameter with
parentheses, which could cause wrong values if the parameter includes
operators.
Also fix the definition of TSIZE_TO_BYTES() so that it actually uses
the parameter. This hasn't caused any problems to date because the
parameter was always been 'tsize'.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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