| 6609916e | 10-Jan-2014 |
Po Liu <po.liu@freescale.com> |
powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi,
powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi, all need the SPL without
section .resetvec.
- Use a clear function name for nand spl boot.
- Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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| 1df99080 | 03-Dec-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8349: Use generic mpc85xx DDR driver
MPC8349 has been using mpc85xx DDR driver through a symbolic link to
mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set
under driver/
powerpc/mpc8349: Use generic mpc85xx DDR driver
MPC8349 has been using mpc85xx DDR driver through a symbolic link to
mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set
under driver/ddr/fsl/, the link is replaced by referring driver
directly. We now can simply enable the macro and use the driver.
Other mpc83xx SoCs still use their own driver.
Signed-off-by: York Sun <yorksun@freescale.com>
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| e88f421e | 28-Nov-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
T4240: Address T4240/T4160 Rev2.0 DDR clock change
MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
It's 12 in Rev1.0, for Rev2.0 it uses 6.
Signed-off-by: Roy Zang <tie-fei.
T4240: Address T4240/T4160 Rev2.0 DDR clock change
MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
It's 12 in Rev1.0, for Rev2.0 it uses 6.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
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| 629d6b32 | 22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T2080/T2081 SoC support
Add support for Freescale T2080/T2081 SoC.
T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 core
powerpc/mpc85xx: Add T2080/T2081 SoC support
Add support for Freescale T2080/T2081 SoC.
T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 16 8
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
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| 51abee64 | 23-Oct-2013 |
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> |
powerpc/85xx: fix broken cpu "clock-frequency" property
When indexing freqProcessor[] we use the first
value in the cpu's "reg" property, which on
new e6500 cores IDs the threads.
But freqProcessor[
powerpc/85xx: fix broken cpu "clock-frequency" property
When indexing freqProcessor[] we use the first
value in the cpu's "reg" property, which on
new e6500 cores IDs the threads.
But freqProcessor[] should be indexed with a
core index so, when fixing "the clock-frequency"
cpu node property, access the freqProcessor[]
with the core index derived from the "reg' property.
If we don't do this, last half of the "cpu" nodes
will have broken "clock-frequency" values.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: York Sun <yorksun@freescale.com>
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| 8f9fe660 | 23-Oct-2013 |
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> |
powerpc/t4240: fix per pci endpoint liodn offsets
Update the code that builds the pci endpoint liodn
offset list so that it doesn't overlap with other
liodns and doesn't generate negative offsets li
powerpc/t4240: fix per pci endpoint liodn offsets
Update the code that builds the pci endpoint liodn
offset list so that it doesn't overlap with other
liodns and doesn't generate negative offsets like:
fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf
0xffffffd1 0xffffffd3
0xffffffd5 0xffffffd7
0xffffffd9 0xffffffdb>;
The update consists in adding a parameter to the
function that builds the list to specify the base
liodn.
On PCI v2.4 use the old base = 256 and, on PCI 3.0
where some of the PCIE liodns are larger than 256,
use a base = 1024. The version check is based on
the PCI controller's version register.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: York Sun <yorksun@freescale.com>
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