1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * Author: Dipen Dudhat <dipen.dudhat@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __FSL_IFC_H 9 #define __FSL_IFC_H 10 11 #ifdef CONFIG_FSL_IFC 12 #include <config.h> 13 #include <common.h> 14 15 /* 16 * CSPR - Chip Select Property Register 17 */ 18 #define CSPR_BA 0xFFFF0000 19 #define CSPR_BA_SHIFT 16 20 #define CSPR_PORT_SIZE 0x00000180 21 #define CSPR_PORT_SIZE_SHIFT 7 22 /* Port Size 8 bit */ 23 #define CSPR_PORT_SIZE_8 0x00000080 24 /* Port Size 16 bit */ 25 #define CSPR_PORT_SIZE_16 0x00000100 26 /* Port Size 32 bit */ 27 #define CSPR_PORT_SIZE_32 0x00000180 28 /* Write Protect */ 29 #define CSPR_WP 0x00000040 30 #define CSPR_WP_SHIFT 6 31 /* Machine Select */ 32 #define CSPR_MSEL 0x00000006 33 #define CSPR_MSEL_SHIFT 1 34 /* NOR */ 35 #define CSPR_MSEL_NOR 0x00000000 36 /* NAND */ 37 #define CSPR_MSEL_NAND 0x00000002 38 /* GPCM */ 39 #define CSPR_MSEL_GPCM 0x00000004 40 /* Bank Valid */ 41 #define CSPR_V 0x00000001 42 #define CSPR_V_SHIFT 0 43 44 /* Convert an address into the right format for the CSPR Registers */ 45 #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) 46 47 /* 48 * Address Mask Register 49 */ 50 #define IFC_AMASK_MASK 0xFFFF0000 51 #define IFC_AMASK_SHIFT 16 52 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ 53 (__ilog2(n) - IFC_AMASK_SHIFT)) 54 55 /* 56 * Chip Select Option Register IFC_NAND Machine 57 */ 58 /* Enable ECC Encoder */ 59 #define CSOR_NAND_ECC_ENC_EN 0x80000000 60 #define CSOR_NAND_ECC_MODE_MASK 0x30000000 61 /* 4 bit correction per 520 Byte sector */ 62 #define CSOR_NAND_ECC_MODE_4 0x00000000 63 /* 8 bit correction per 528 Byte sector */ 64 #define CSOR_NAND_ECC_MODE_8 0x10000000 65 /* Enable ECC Decoder */ 66 #define CSOR_NAND_ECC_DEC_EN 0x04000000 67 /* Row Address Length */ 68 #define CSOR_NAND_RAL_MASK 0x01800000 69 #define CSOR_NAND_RAL_SHIFT 20 70 #define CSOR_NAND_RAL_1 0x00000000 71 #define CSOR_NAND_RAL_2 0x00800000 72 #define CSOR_NAND_RAL_3 0x01000000 73 #define CSOR_NAND_RAL_4 0x01800000 74 /* Page Size 512b, 2k, 4k */ 75 #define CSOR_NAND_PGS_MASK 0x00180000 76 #define CSOR_NAND_PGS_SHIFT 16 77 #define CSOR_NAND_PGS_512 0x00000000 78 #define CSOR_NAND_PGS_2K 0x00080000 79 #define CSOR_NAND_PGS_4K 0x00100000 80 /* Spare region Size */ 81 #define CSOR_NAND_SPRZ_MASK 0x0000E000 82 #define CSOR_NAND_SPRZ_SHIFT 13 83 #define CSOR_NAND_SPRZ_16 0x00000000 84 #define CSOR_NAND_SPRZ_64 0x00002000 85 #define CSOR_NAND_SPRZ_128 0x00004000 86 #define CSOR_NAND_SPRZ_210 0x00006000 87 #define CSOR_NAND_SPRZ_218 0x00008000 88 #define CSOR_NAND_SPRZ_224 0x0000A000 89 /* Pages Per Block */ 90 #define CSOR_NAND_PB_MASK 0x00000700 91 #define CSOR_NAND_PB_SHIFT 8 92 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) 93 /* Time for Read Enable High to Output High Impedance */ 94 #define CSOR_NAND_TRHZ_MASK 0x0000001C 95 #define CSOR_NAND_TRHZ_SHIFT 2 96 #define CSOR_NAND_TRHZ_20 0x00000000 97 #define CSOR_NAND_TRHZ_40 0x00000004 98 #define CSOR_NAND_TRHZ_60 0x00000008 99 #define CSOR_NAND_TRHZ_80 0x0000000C 100 #define CSOR_NAND_TRHZ_100 0x00000010 101 /* Buffer control disable */ 102 #define CSOR_NAND_BCTLD 0x00000001 103 104 /* 105 * Chip Select Option Register - NOR Flash Mode 106 */ 107 /* Enable Address shift Mode */ 108 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 109 /* Page Read Enable from NOR device */ 110 #define CSOR_NOR_PGRD_EN 0x10000000 111 /* AVD Toggle Enable during Burst Program */ 112 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 113 /* Address Data Multiplexing Shift */ 114 #define CSOR_NOR_ADM_MASK 0x0003E000 115 #define CSOR_NOR_ADM_SHIFT_SHIFT 13 116 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) 117 /* Type of the NOR device hooked */ 118 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 119 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 120 /* Time for Read Enable High to Output High Impedance */ 121 #define CSOR_NOR_TRHZ_MASK 0x0000001C 122 #define CSOR_NOR_TRHZ_SHIFT 2 123 #define CSOR_NOR_TRHZ_20 0x00000000 124 #define CSOR_NOR_TRHZ_40 0x00000004 125 #define CSOR_NOR_TRHZ_60 0x00000008 126 #define CSOR_NOR_TRHZ_80 0x0000000C 127 #define CSOR_NOR_TRHZ_100 0x00000010 128 /* Buffer control disable */ 129 #define CSOR_NOR_BCTLD 0x00000001 130 131 /* 132 * Chip Select Option Register - GPCM Mode 133 */ 134 /* GPCM Mode - Normal */ 135 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000 136 /* GPCM Mode - GenericASIC */ 137 #define CSOR_GPCM_GPMODE_ASIC 0x80000000 138 /* Parity Mode odd/even */ 139 #define CSOR_GPCM_PARITY_EVEN 0x40000000 140 /* Parity Checking enable/disable */ 141 #define CSOR_GPCM_PAR_EN 0x20000000 142 /* GPCM Timeout Count */ 143 #define CSOR_GPCM_GPTO_MASK 0x0F000000 144 #define CSOR_GPCM_GPTO_SHIFT 24 145 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) 146 /* GPCM External Access Termination mode for read access */ 147 #define CSOR_GPCM_RGETA_EXT 0x00080000 148 /* GPCM External Access Termination mode for write access */ 149 #define CSOR_GPCM_WGETA_EXT 0x00040000 150 /* Address Data Multiplexing Shift */ 151 #define CSOR_GPCM_ADM_MASK 0x0003E000 152 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13 153 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) 154 /* Generic ASIC Parity error indication delay */ 155 #define CSOR_GPCM_GAPERRD_MASK 0x00000180 156 #define CSOR_GPCM_GAPERRD_SHIFT 7 157 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) 158 /* Time for Read Enable High to Output High Impedance */ 159 #define CSOR_GPCM_TRHZ_MASK 0x0000001C 160 #define CSOR_GPCM_TRHZ_20 0x00000000 161 #define CSOR_GPCM_TRHZ_40 0x00000004 162 #define CSOR_GPCM_TRHZ_60 0x00000008 163 #define CSOR_GPCM_TRHZ_80 0x0000000C 164 #define CSOR_GPCM_TRHZ_100 0x00000010 165 /* Buffer control disable */ 166 #define CSOR_GPCM_BCTLD 0x00000001 167 168 /* 169 * Flash Timing Registers (FTIM0 - FTIM2_CSn) 170 */ 171 /* 172 * FTIM0 - NAND Flash Mode 173 */ 174 #define FTIM0_NAND 0x7EFF3F3F 175 #define FTIM0_NAND_TCCST_SHIFT 25 176 #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) 177 #define FTIM0_NAND_TWP_SHIFT 16 178 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) 179 #define FTIM0_NAND_TWCHT_SHIFT 8 180 #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) 181 #define FTIM0_NAND_TWH_SHIFT 0 182 #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) 183 /* 184 * FTIM1 - NAND Flash Mode 185 */ 186 #define FTIM1_NAND 0xFFFF3FFF 187 #define FTIM1_NAND_TADLE_SHIFT 24 188 #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) 189 #define FTIM1_NAND_TWBE_SHIFT 16 190 #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) 191 #define FTIM1_NAND_TRR_SHIFT 8 192 #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) 193 #define FTIM1_NAND_TRP_SHIFT 0 194 #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) 195 /* 196 * FTIM2 - NAND Flash Mode 197 */ 198 #define FTIM2_NAND 0x1FE1F8FF 199 #define FTIM2_NAND_TRAD_SHIFT 21 200 #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) 201 #define FTIM2_NAND_TREH_SHIFT 11 202 #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) 203 #define FTIM2_NAND_TWHRE_SHIFT 0 204 #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) 205 /* 206 * FTIM3 - NAND Flash Mode 207 */ 208 #define FTIM3_NAND 0xFF000000 209 #define FTIM3_NAND_TWW_SHIFT 24 210 #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) 211 212 /* 213 * FTIM0 - NOR Flash Mode 214 */ 215 #define FTIM0_NOR 0xF03F3F3F 216 #define FTIM0_NOR_TACSE_SHIFT 28 217 #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) 218 #define FTIM0_NOR_TEADC_SHIFT 16 219 #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) 220 #define FTIM0_NOR_TAVDS_SHIFT 8 221 #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) 222 #define FTIM0_NOR_TEAHC_SHIFT 0 223 #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) 224 /* 225 * FTIM1 - NOR Flash Mode 226 */ 227 #define FTIM1_NOR 0xFF003F3F 228 #define FTIM1_NOR_TACO_SHIFT 24 229 #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) 230 #define FTIM1_NOR_TRAD_NOR_SHIFT 8 231 #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) 232 #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 233 #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) 234 /* 235 * FTIM2 - NOR Flash Mode 236 */ 237 #define FTIM2_NOR 0x0F3CFCFF 238 #define FTIM2_NOR_TCS_SHIFT 24 239 #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) 240 #define FTIM2_NOR_TCH_SHIFT 18 241 #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) 242 #define FTIM2_NOR_TWPH_SHIFT 10 243 #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) 244 #define FTIM2_NOR_TWP_SHIFT 0 245 #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) 246 247 /* 248 * FTIM0 - Normal GPCM Mode 249 */ 250 #define FTIM0_GPCM 0xF03F3F3F 251 #define FTIM0_GPCM_TACSE_SHIFT 28 252 #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) 253 #define FTIM0_GPCM_TEADC_SHIFT 16 254 #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) 255 #define FTIM0_GPCM_TAVDS_SHIFT 8 256 #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) 257 #define FTIM0_GPCM_TEAHC_SHIFT 0 258 #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) 259 /* 260 * FTIM1 - Normal GPCM Mode 261 */ 262 #define FTIM1_GPCM 0xFF003F00 263 #define FTIM1_GPCM_TACO_SHIFT 24 264 #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) 265 #define FTIM1_GPCM_TRAD_SHIFT 8 266 #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) 267 /* 268 * FTIM2 - Normal GPCM Mode 269 */ 270 #define FTIM2_GPCM 0x0F3C00FF 271 #define FTIM2_GPCM_TCS_SHIFT 24 272 #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) 273 #define FTIM2_GPCM_TCH_SHIFT 18 274 #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) 275 #define FTIM2_GPCM_TWP_SHIFT 0 276 #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) 277 278 /* 279 * Ready Busy Status Register (RB_STAT) 280 */ 281 /* CSn is READY */ 282 #define IFC_RB_STAT_READY_CS0 0x80000000 283 #define IFC_RB_STAT_READY_CS1 0x40000000 284 #define IFC_RB_STAT_READY_CS2 0x20000000 285 #define IFC_RB_STAT_READY_CS3 0x10000000 286 287 /* 288 * General Control Register (GCR) 289 */ 290 #define IFC_GCR_MASK 0x8000F800 291 /* reset all IFC hardware */ 292 #define IFC_GCR_SOFT_RST_ALL 0x80000000 293 /* Turnaroud Time of external buffer */ 294 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 295 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 296 297 /* 298 * Common Event and Error Status Register (CM_EVTER_STAT) 299 */ 300 /* Chip select error */ 301 #define IFC_CM_EVTER_STAT_CSER 0x80000000 302 303 /* 304 * Common Event and Error Enable Register (CM_EVTER_EN) 305 */ 306 /* Chip select error checking enable */ 307 #define IFC_CM_EVTER_EN_CSEREN 0x80000000 308 309 /* 310 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) 311 */ 312 /* Chip select error interrupt enable */ 313 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 314 315 /* 316 * Common Transfer Error Attribute Register-0 (CM_ERATTR0) 317 */ 318 /* transaction type of error Read/Write */ 319 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 320 #define IFC_CM_ERATTR0_ERAID 0x0FF00000 321 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00 322 323 /* 324 * Clock Control Register (CCR) 325 */ 326 #define IFC_CCR_MASK 0x0F0F8800 327 /* Clock division ratio */ 328 #define IFC_CCR_CLK_DIV_MASK 0x0F000000 329 #define IFC_CCR_CLK_DIV_SHIFT 24 330 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) 331 /* IFC Clock Delay */ 332 #define IFC_CCR_CLK_DLY_MASK 0x000F0000 333 #define IFC_CCR_CLK_DLY_SHIFT 16 334 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) 335 /* Invert IFC clock before sending out */ 336 #define IFC_CCR_INV_CLK_EN 0x00008000 337 /* Fedback IFC Clock */ 338 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 339 340 /* 341 * Clock Status Register (CSR) 342 */ 343 /* Clk is stable */ 344 #define IFC_CSR_CLK_STAT_STABLE 0x80000000 345 346 /* 347 * IFC_NAND Machine Specific Registers 348 */ 349 /* 350 * NAND Configuration Register (NCFGR) 351 */ 352 /* Auto Boot Mode */ 353 #define IFC_NAND_NCFGR_BOOT 0x80000000 354 /* Addressing Mode-ROW0+n/COL0 */ 355 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 356 /* Addressing Mode-ROW0+n/COL0+n */ 357 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 358 /* Number of loop iterations of FIR sequences for multi page operations */ 359 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 360 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 361 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) 362 /* Number of wait cycles */ 363 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF 364 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 365 366 /* 367 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) 368 */ 369 /* General purpose FCM flash command bytes CMD0-CMD7 */ 370 #define IFC_NAND_FCR0_CMD0 0xFF000000 371 #define IFC_NAND_FCR0_CMD0_SHIFT 24 372 #define IFC_NAND_FCR0_CMD1 0x00FF0000 373 #define IFC_NAND_FCR0_CMD1_SHIFT 16 374 #define IFC_NAND_FCR0_CMD2 0x0000FF00 375 #define IFC_NAND_FCR0_CMD2_SHIFT 8 376 #define IFC_NAND_FCR0_CMD3 0x000000FF 377 #define IFC_NAND_FCR0_CMD3_SHIFT 0 378 #define IFC_NAND_FCR1_CMD4 0xFF000000 379 #define IFC_NAND_FCR1_CMD4_SHIFT 24 380 #define IFC_NAND_FCR1_CMD5 0x00FF0000 381 #define IFC_NAND_FCR1_CMD5_SHIFT 16 382 #define IFC_NAND_FCR1_CMD6 0x0000FF00 383 #define IFC_NAND_FCR1_CMD6_SHIFT 8 384 #define IFC_NAND_FCR1_CMD7 0x000000FF 385 #define IFC_NAND_FCR1_CMD7_SHIFT 0 386 387 /* 388 * Flash ROW and COL Address Register (ROWn, COLn) 389 */ 390 /* Main/spare region locator */ 391 #define IFC_NAND_COL_MS 0x80000000 392 /* Column Address */ 393 #define IFC_NAND_COL_CA_MASK 0x00000FFF 394 395 /* 396 * NAND Flash Byte Count Register (NAND_BC) 397 */ 398 /* Byte Count for read/Write */ 399 #define IFC_NAND_BC 0x000001FF 400 401 /* 402 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) 403 */ 404 /* NAND Machine specific opcodes OP0-OP14*/ 405 #define IFC_NAND_FIR0_OP0 0xFC000000 406 #define IFC_NAND_FIR0_OP0_SHIFT 26 407 #define IFC_NAND_FIR0_OP1 0x03F00000 408 #define IFC_NAND_FIR0_OP1_SHIFT 20 409 #define IFC_NAND_FIR0_OP2 0x000FC000 410 #define IFC_NAND_FIR0_OP2_SHIFT 14 411 #define IFC_NAND_FIR0_OP3 0x00003F00 412 #define IFC_NAND_FIR0_OP3_SHIFT 8 413 #define IFC_NAND_FIR0_OP4 0x000000FC 414 #define IFC_NAND_FIR0_OP4_SHIFT 2 415 #define IFC_NAND_FIR1_OP5 0xFC000000 416 #define IFC_NAND_FIR1_OP5_SHIFT 26 417 #define IFC_NAND_FIR1_OP6 0x03F00000 418 #define IFC_NAND_FIR1_OP6_SHIFT 20 419 #define IFC_NAND_FIR1_OP7 0x000FC000 420 #define IFC_NAND_FIR1_OP7_SHIFT 14 421 #define IFC_NAND_FIR1_OP8 0x00003F00 422 #define IFC_NAND_FIR1_OP8_SHIFT 8 423 #define IFC_NAND_FIR1_OP9 0x000000FC 424 #define IFC_NAND_FIR1_OP9_SHIFT 2 425 #define IFC_NAND_FIR2_OP10 0xFC000000 426 #define IFC_NAND_FIR2_OP10_SHIFT 26 427 #define IFC_NAND_FIR2_OP11 0x03F00000 428 #define IFC_NAND_FIR2_OP11_SHIFT 20 429 #define IFC_NAND_FIR2_OP12 0x000FC000 430 #define IFC_NAND_FIR2_OP12_SHIFT 14 431 #define IFC_NAND_FIR2_OP13 0x00003F00 432 #define IFC_NAND_FIR2_OP13_SHIFT 8 433 #define IFC_NAND_FIR2_OP14 0x000000FC 434 #define IFC_NAND_FIR2_OP14_SHIFT 2 435 436 /* 437 * Instruction opcodes to be programmed 438 * in FIR registers- 6bits 439 */ 440 enum ifc_nand_fir_opcodes { 441 IFC_FIR_OP_NOP, 442 IFC_FIR_OP_CA0, 443 IFC_FIR_OP_CA1, 444 IFC_FIR_OP_CA2, 445 IFC_FIR_OP_CA3, 446 IFC_FIR_OP_RA0, 447 IFC_FIR_OP_RA1, 448 IFC_FIR_OP_RA2, 449 IFC_FIR_OP_RA3, 450 IFC_FIR_OP_CMD0, 451 IFC_FIR_OP_CMD1, 452 IFC_FIR_OP_CMD2, 453 IFC_FIR_OP_CMD3, 454 IFC_FIR_OP_CMD4, 455 IFC_FIR_OP_CMD5, 456 IFC_FIR_OP_CMD6, 457 IFC_FIR_OP_CMD7, 458 IFC_FIR_OP_CW0, 459 IFC_FIR_OP_CW1, 460 IFC_FIR_OP_CW2, 461 IFC_FIR_OP_CW3, 462 IFC_FIR_OP_CW4, 463 IFC_FIR_OP_CW5, 464 IFC_FIR_OP_CW6, 465 IFC_FIR_OP_CW7, 466 IFC_FIR_OP_WBCD, 467 IFC_FIR_OP_RBCD, 468 IFC_FIR_OP_BTRD, 469 IFC_FIR_OP_RDSTAT, 470 IFC_FIR_OP_NWAIT, 471 IFC_FIR_OP_WFR, 472 IFC_FIR_OP_SBRD, 473 IFC_FIR_OP_UA, 474 IFC_FIR_OP_RB, 475 }; 476 477 /* 478 * NAND Chip Select Register (NAND_CSEL) 479 */ 480 #define IFC_NAND_CSEL 0x0C000000 481 #define IFC_NAND_CSEL_SHIFT 26 482 #define IFC_NAND_CSEL_CS0 0x00000000 483 #define IFC_NAND_CSEL_CS1 0x04000000 484 #define IFC_NAND_CSEL_CS2 0x08000000 485 #define IFC_NAND_CSEL_CS3 0x0C000000 486 487 /* 488 * NAND Operation Sequence Start (NANDSEQ_STRT) 489 */ 490 /* NAND Flash Operation Start */ 491 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 492 /* Automatic Erase */ 493 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 494 /* Automatic Program */ 495 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 496 /* Automatic Copyback */ 497 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 498 /* Automatic Read Operation */ 499 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 500 /* Automatic Status Read */ 501 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 502 503 /* 504 * NAND Event and Error Status Register (NAND_EVTER_STAT) 505 */ 506 /* Operation Complete */ 507 #define IFC_NAND_EVTER_STAT_OPC 0x80000000 508 /* Flash Timeout Error */ 509 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000 510 /* Write Protect Error */ 511 #define IFC_NAND_EVTER_STAT_WPER 0x04000000 512 /* ECC Error */ 513 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000 514 /* RCW Load Done */ 515 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 516 /* Boot Loadr Done */ 517 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 518 /* Bad Block Indicator search select */ 519 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 520 521 /* 522 * NAND Flash Page Read Completion Event Status Register 523 * (PGRDCMPL_EVT_STAT) 524 */ 525 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 526 /* Small Page 0-15 Done */ 527 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) 528 /* Large Page(2K) 0-3 Done */ 529 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) 530 /* Large Page(4K) 0-1 Done */ 531 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) 532 533 /* 534 * NAND Event and Error Enable Register (NAND_EVTER_EN) 535 */ 536 /* Operation complete event enable */ 537 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 538 /* Page read complete event enable */ 539 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 540 /* Flash Timeout error enable */ 541 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 542 /* Write Protect error enable */ 543 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 544 /* ECC error logging enable */ 545 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 546 547 /* 548 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) 549 */ 550 /* Enable interrupt for operation complete */ 551 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 552 /* Enable interrupt for Page read complete */ 553 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 554 /* Enable interrupt for Flash timeout error */ 555 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 556 /* Enable interrupt for Write protect error */ 557 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 558 /* Enable interrupt for ECC error*/ 559 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 560 561 /* 562 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) 563 */ 564 #define IFC_NAND_ERATTR0_MASK 0x0C080000 565 /* Error on CS0-3 for NAND */ 566 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 567 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 568 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 569 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 570 /* Transaction type of error Read/Write */ 571 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 572 573 /* 574 * NAND Flash Status Register (NAND_FSR) 575 */ 576 /* First byte of data read from read status op */ 577 #define IFC_NAND_NFSR_RS0 0xFF000000 578 /* Second byte of data read from read status op */ 579 #define IFC_NAND_NFSR_RS1 0x00FF0000 580 581 /* 582 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) 583 */ 584 /* Number of ECC errors on sector n (n = 0-15) */ 585 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 586 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 587 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 588 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 589 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 590 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 591 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F 592 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 593 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 594 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 595 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 596 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 597 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 598 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 599 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F 600 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 601 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 602 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 603 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 604 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 605 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 606 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 607 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F 608 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 609 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 610 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 611 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 612 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 613 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 614 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 615 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F 616 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 617 618 /* 619 * NAND Control Register (NANDCR) 620 */ 621 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 622 #define IFC_NAND_NCR_FTOCNT_SHIFT 25 623 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) 624 625 /* 626 * NAND_AUTOBOOT_TRGR 627 */ 628 /* Trigger RCW load */ 629 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 630 /* Trigget Auto Boot */ 631 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 632 633 /* 634 * NAND_MDR 635 */ 636 /* 1st read data byte when opcode SBRD */ 637 #define IFC_NAND_MDR_RDATA0 0xFF000000 638 /* 2nd read data byte when opcode SBRD */ 639 #define IFC_NAND_MDR_RDATA1 0x00FF0000 640 641 /* 642 * NOR Machine Specific Registers 643 */ 644 /* 645 * NOR Event and Error Status Register (NOR_EVTER_STAT) 646 */ 647 /* NOR Command Sequence Operation Complete */ 648 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 649 /* Write Protect Error */ 650 #define IFC_NOR_EVTER_STAT_WPER 0x04000000 651 /* Command Sequence Timeout Error */ 652 #define IFC_NOR_EVTER_STAT_STOER 0x01000000 653 654 /* 655 * NOR Event and Error Enable Register (NOR_EVTER_EN) 656 */ 657 /* NOR Command Seq complete event enable */ 658 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 659 /* Write Protect Error Checking Enable */ 660 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000 661 /* Timeout Error Enable */ 662 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000 663 664 /* 665 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) 666 */ 667 /* Enable interrupt for OPC complete */ 668 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 669 /* Enable interrupt for write protect error */ 670 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 671 /* Enable interrupt for timeout error */ 672 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 673 674 /* 675 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) 676 */ 677 /* Source ID for error transaction */ 678 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 679 /* AXI ID for error transation */ 680 #define IFC_NOR_ERATTR0_ERAID 0x000FF000 681 /* Chip select corresponds to NOR error */ 682 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 683 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 684 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 685 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 686 /* Type of transaction read/write */ 687 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 688 689 /* 690 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) 691 */ 692 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 693 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 694 695 /* 696 * NOR Control Register (NORCR) 697 */ 698 #define IFC_NORCR_MASK 0x0F0F0000 699 /* No. of Address/Data Phase */ 700 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 701 #define IFC_NORCR_NUM_PHASE_SHIFT 24 702 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) 703 /* Sequence Timeout Count */ 704 #define IFC_NORCR_STOCNT_MASK 0x000F0000 705 #define IFC_NORCR_STOCNT_SHIFT 16 706 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) 707 708 /* 709 * GPCM Machine specific registers 710 */ 711 /* 712 * GPCM Event and Error Status Register (GPCM_EVTER_STAT) 713 */ 714 /* Timeout error */ 715 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000 716 /* Parity error */ 717 #define IFC_GPCM_EVTER_STAT_PER 0x01000000 718 719 /* 720 * GPCM Event and Error Enable Register (GPCM_EVTER_EN) 721 */ 722 /* Timeout error enable */ 723 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 724 /* Parity error enable */ 725 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 726 727 /* 728 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) 729 */ 730 /* Enable Interrupt for timeout error */ 731 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 732 /* Enable Interrupt for Parity error */ 733 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000 734 735 /* 736 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) 737 */ 738 /* Source ID for error transaction */ 739 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 740 /* AXI ID for error transaction */ 741 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000 742 /* Chip select corresponds to GPCM error */ 743 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 744 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 745 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 746 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 747 /* Type of transaction read/Write */ 748 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 749 750 /* 751 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) 752 */ 753 /* On which beat of address/data parity error is observed */ 754 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 755 /* Parity Error on byte */ 756 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 757 /* Parity Error reported in addr or data phase */ 758 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 759 760 /* 761 * GPCM Status Register (GPCM_STAT) 762 */ 763 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ 764 765 766 #ifndef __ASSEMBLY__ 767 #include <asm/io.h> 768 769 extern void print_ifc_regs(void); 770 extern void init_early_memctl_regs(void); 771 772 #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) 773 774 #define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) 775 #define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) 776 #define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) 777 #define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) 778 #define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) 779 #define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) 780 781 #define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) 782 #define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) 783 #define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) 784 #define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) 785 #define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) 786 #define set_ifc_ftim(i, j, v) \ 787 (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) 788 789 enum ifc_chip_sel { 790 IFC_CS0, 791 IFC_CS1, 792 IFC_CS2, 793 IFC_CS3, 794 IFC_CS4, 795 IFC_CS5, 796 IFC_CS6, 797 IFC_CS7, 798 }; 799 800 enum ifc_ftims { 801 IFC_FTIM0, 802 IFC_FTIM1, 803 IFC_FTIM2, 804 IFC_FTIM3, 805 }; 806 807 /* 808 * IFC Controller NAND Machine registers 809 */ 810 struct fsl_ifc_nand { 811 u32 ncfgr; 812 u32 res1[0x4]; 813 u32 nand_fcr0; 814 u32 nand_fcr1; 815 u32 res2[0x8]; 816 u32 row0; 817 u32 res3; 818 u32 col0; 819 u32 res4; 820 u32 row1; 821 u32 res5; 822 u32 col1; 823 u32 res6; 824 u32 row2; 825 u32 res7; 826 u32 col2; 827 u32 res8; 828 u32 row3; 829 u32 res9; 830 u32 col3; 831 u32 res10[0x24]; 832 u32 nand_fbcr; 833 u32 res11; 834 u32 nand_fir0; 835 u32 nand_fir1; 836 u32 nand_fir2; 837 u32 res12[0x10]; 838 u32 nand_csel; 839 u32 res13; 840 u32 nandseq_strt; 841 u32 res14; 842 u32 nand_evter_stat; 843 u32 res15; 844 u32 pgrdcmpl_evt_stat; 845 u32 res16[0x2]; 846 u32 nand_evter_en; 847 u32 res17[0x2]; 848 u32 nand_evter_intr_en; 849 u32 res18[0x2]; 850 u32 nand_erattr0; 851 u32 nand_erattr1; 852 u32 res19[0x10]; 853 u32 nand_fsr; 854 u32 res20; 855 u32 nand_eccstat[4]; 856 u32 res21[0x20]; 857 u32 nanndcr; 858 u32 res22[0x2]; 859 u32 nand_autoboot_trgr; 860 u32 res23; 861 u32 nand_mdr; 862 u32 res24[0x5C]; 863 }; 864 865 /* 866 * IFC controller NOR Machine registers 867 */ 868 struct fsl_ifc_nor { 869 u32 nor_evter_stat; 870 u32 res1[0x2]; 871 u32 nor_evter_en; 872 u32 res2[0x2]; 873 u32 nor_evter_intr_en; 874 u32 res3[0x2]; 875 u32 nor_erattr0; 876 u32 nor_erattr1; 877 u32 nor_erattr2; 878 u32 res4[0x4]; 879 u32 norcr; 880 u32 res5[0xEF]; 881 }; 882 883 /* 884 * IFC controller GPCM Machine registers 885 */ 886 struct fsl_ifc_gpcm { 887 u32 gpcm_evter_stat; 888 u32 res1[0x2]; 889 u32 gpcm_evter_en; 890 u32 res2[0x2]; 891 u32 gpcm_evter_intr_en; 892 u32 res3[0x2]; 893 u32 gpcm_erattr0; 894 u32 gpcm_erattr1; 895 u32 gpcm_erattr2; 896 u32 gpcm_stat; 897 u32 res4[0x1F3]; 898 }; 899 900 #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT 901 #if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) 902 #define IFC_CSPR_REG_LEN 148 903 #define IFC_AMASK_REG_LEN 144 904 #define IFC_CSOR_REG_LEN 144 905 #define IFC_FTIM_REG_LEN 576 906 907 #define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \ 908 CONFIG_SYS_FSL_IFC_BANK_COUNT 909 #define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \ 910 CONFIG_SYS_FSL_IFC_BANK_COUNT 911 #define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \ 912 CONFIG_SYS_FSL_IFC_BANK_COUNT 913 #define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \ 914 CONFIG_SYS_FSL_IFC_BANK_COUNT 915 #else 916 #error IFC BANK count not vaild 917 #endif 918 #else 919 #error IFC BANK count not defined 920 #endif 921 922 struct fsl_ifc_cspr { 923 u32 cspr_ext; 924 u32 cspr; 925 u32 res; 926 }; 927 928 struct fsl_ifc_amask { 929 u32 amask; 930 u32 res[0x2]; 931 }; 932 933 struct fsl_ifc_csor { 934 u32 csor; 935 u32 csor_ext; 936 u32 res; 937 }; 938 939 struct fsl_ifc_ftim { 940 u32 ftim[4]; 941 u32 res[0x8]; 942 }; 943 944 /* 945 * IFC Controller Registers 946 */ 947 struct fsl_ifc { 948 u32 ifc_rev; 949 u32 res1[0x2]; 950 struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 951 u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; 952 struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 953 u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; 954 struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 955 u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; 956 struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 957 u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; 958 u32 rb_stat; 959 u32 res6[0x2]; 960 u32 ifc_gcr; 961 u32 res7[0x2]; 962 u32 cm_evter_stat; 963 u32 res8[0x2]; 964 u32 cm_evter_en; 965 u32 res9[0x2]; 966 u32 cm_evter_intr_en; 967 u32 res10[0x2]; 968 u32 cm_erattr0; 969 u32 cm_erattr1; 970 u32 res11[0x2]; 971 u32 ifc_ccr; 972 u32 ifc_csr; 973 u32 res12[0x2EB]; 974 struct fsl_ifc_nand ifc_nand; 975 struct fsl_ifc_nor ifc_nor; 976 struct fsl_ifc_gpcm ifc_gpcm; 977 }; 978 979 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 980 #undef CSPR_MSEL_NOR 981 #define CSPR_MSEL_NOR CSPR_MSEL_GPCM 982 #endif 983 #endif /* CONFIG_FSL_IFC */ 984 985 #endif /* __ASSEMBLY__ */ 986 #endif /* __FSL_IFC_H */ 987