| 6ece2550 | 21-May-2010 |
Kumar Gala <galak@kernel.crashing.org> |
Convert Makefiles from COBJS-${} to COBJS-$()
Match style we use almost everywhere else
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
| 71bd860c | 19-May-2010 |
Kim Phillips <kim.phillips@freescale.com> |
mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c
commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx:
retain POR values of non-configured ACR, SPCR, SCCR, and LCRR
mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c
commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx:
retain POR values of non-configured ACR, SPCR, SCCR, and LCRR
bitfields" incorrectly shifted <register>_<bitfield> (e.g.
ACR_PIPE_DEP) values that were preshifted by their
definition in mpc83xx.h.
this patch removes the unnecessary shifting for the newly
utilized mask values in cpu_init.c, and prevents seemingly
unrelated symptoms such as an mpc8379erdb board from
locking up whilst performing a networking operation,
e.g. a tftp.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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|
| f6970d0c | 18-May-2010 |
Horst Kronstorfer <hkronsto@frequentis.com> |
Fixed two typos in arch/powerpc/cpu/mpc83xx/start.S.
Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
| 568278e3 | 17-May-2010 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx |
| a4bfc4cc | 14-May-2010 |
Kim Phillips <kim.phillips@freescale.com> |
mpc83xx: fix NAND bootstrap too big error
commit 167cdad1372917bc11c636c359aad02625291fa9 "SERIAL: Enable
port-mapped access" inadvertently broke 83xx nand boards by
converting NS16550_init to use i
mpc83xx: fix NAND bootstrap too big error
commit 167cdad1372917bc11c636c359aad02625291fa9 "SERIAL: Enable
port-mapped access" inadvertently broke 83xx nand boards by
converting NS16550_init to use io accessors, which expanded
the size of the generated code.
this patch fixes the problem by removing icache functions from
the nand builds, which somewhat follows commit
1a2e203b31d33fb720f2cf1033b241ad36ab405a "mpc83xx: turn on icache
in core initialization to improve u-boot boot time"
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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|
| bcb6c2bb | 07-May-2010 |
York Sun <yorksun@freescale.com> |
Enabled support for Rev 1.3 SPD for DDR2 DIMMs
SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3.
The difference has ben examined and the code is compatible.
Speed bins is not ver
Enabled support for Rev 1.3 SPD for DDR2 DIMMs
SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3.
The difference has ben examined and the code is compatible.
Speed bins is not verified on hardware for CL7 at this moment.
This patch also enables SPD Rev 1.x where x is up to "F". According to SPD
spec, the lower nibble is optionally used to determine which additinal bytes
or attribute bits have been defined. Software can safely use defaults. However,
the upper nibble should always be checked.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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|
| f54fe87a | 20-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled
On the MPC85xx platform if we have SATA its connected on SERDES.
Determing if SATA is enabled via sata_initialize should not
85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled
On the MPC85xx platform if we have SATA its connected on SERDES.
Determing if SATA is enabled via sata_initialize should not be board
specific and thus we move it out of the MPC8536DS board code.
Additionally, now that we have is_serdes_configured() we can determine
if the given SATA port is enabled and error out if its not in the
driver.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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|
| 54648985 | 20-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled
The new is_serdes_configured covers a broader range of devices than the
PCI specific code. Use it instead as we convert away
85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled
The new is_serdes_configured covers a broader range of devices than the
PCI specific code. Use it instead as we convert away from the
is_fsl_pci_cfg() code.
Additionally move to setting LAWs for PCI based on if its configured.
Also updated PCI FDT fixup code to remove PCI controllers from dtb if
they are configured.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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|
| 6ab4011b | 20-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
85xx: Add is_serdes_configured() support to MPC8536 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since the
85xx: Add is_serdes_configured() support to MPC8536 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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|
| e4a95d11 | 28-Apr-2010 |
Stefan Roese <sr@denx.de> |
powerpc: Consolidate bootcount_{store|load} for PowerPC
This patch consolidates bootcount_{store|load} for PowerPC by
implementing a common version in arch/powerpc/lib/bootcount.c. This
code is now
powerpc: Consolidate bootcount_{store|load} for PowerPC
This patch consolidates bootcount_{store|load} for PowerPC by
implementing a common version in arch/powerpc/lib/bootcount.c. This
code is now used by all PowerPC variants that currently have these
functions implemented.
The functions now use the proper IO-accessor functions to read/write the
values.
This code also supports two different bootcount versions:
a) Use 2 separate words (2 * 32bit) to store the bootcounter
b) Use only 1 word (2 * 16bit) to store the bootcounter
Version b) was already used by MPC5xxx.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
for 83xx parts
Cc: Michael Zaidman <michael.zaidman@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Anatolij Gustschin <agust@denx.de>
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|
| 6f5f89f0 | 01-Apr-2010 |
Detlev Zundel <dzu@denx.de> |
Remove unused "local_crc32" function.
For code archeologists, this is a nice example of copy and paste history.
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Ben Warren <biggerbadderben
Remove unused "local_crc32" function.
For code archeologists, this is a nice example of copy and paste history.
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
show more ...
|
| d03f4230 | 27-Apr-2010 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx |
| 8e98f5f7 | 27-Apr-2010 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx |
| c303176a | 27-Apr-2010 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx |
| 7e1afb62 | 20-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQ
The MPC83xx SERDES control is different from the other FSL PPC chips.
For now lets split it out so we can standardize on interfaces for
dete
ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQ
The MPC83xx SERDES control is different from the other FSL PPC chips.
For now lets split it out so we can standardize on interfaces for
determining of a device on SERDES is configured.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
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|
| 3f0202ed | 21-Apr-2010 |
Lan Chunhe <b25806@freescale.com> |
mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flash
Signed-off-by: Lan Chunhe <b25806@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar
mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flash
Signed-off-by: Lan Chunhe <b25806@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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|
| 0c955daf | 14-Apr-2010 |
Dave Liu <daveliu@freescale.com> |
85xx: clean up the io_sel for PCI express of P1022
clean up the wrong io_sel for PCI express according to latest manual.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <g
85xx: clean up the io_sel for PCI express of P1022
clean up the wrong io_sel for PCI express according to latest manual.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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|
| 9ce3c228 | 13-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
85xx: Fix compile warning
cpu.c: In function 'checkcpu':
cpu.c:47: warning: unused variable 'gur'
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
| 4db9708b | 14-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
85xx: Convert cpu_init_f code to use out_be32 for LBC registers
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
| 99bac479 | 08-Dec-2009 |
Dave Liu <daveliu@freescale.com> |
fsl-ddr: Add extra cycle to turnaround times
Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-of
fsl-ddr: Add extra cycle to turnaround times
Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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|
| ab48ca1a | 10-Feb-2010 |
Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
ppc/p4080: Fix synchronous frequency calculations
When DDR is in synchronous mode, the existing code assigns sysclk
frequency to DDR frequency. It should be synchronous with the platform
frequency.
ppc/p4080: Fix synchronous frequency calculations
When DDR is in synchronous mode, the existing code assigns sysclk
frequency to DDR frequency. It should be synchronous with the platform
frequency. CPU frequency is based on platform frequency in synchronous
mode.
Also fix:
* Fixes the bit mask for DDR_SYNC (RCWSR5[184])
* Corrects the detection of synchronous mode.
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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|
| 2ebdb9a9 | 24-Apr-2010 |
Anatolij Gustschin <agust@denx.de> |
mpc5121: add common post_word_load/store code
Add common post_word_load/post_word_store routines
for all mpc5121 boards. pdm360ng board POST support
added by subsequent patch needs them.
Signed-off
mpc5121: add common post_word_load/store code
Add common post_word_load/post_word_store routines
for all mpc5121 boards. pdm360ng board POST support
added by subsequent patch needs them.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
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|
| a3921eef | 24-Apr-2010 |
Anatolij Gustschin <agust@denx.de> |
mpc5121: add support for PDM360NG board
PDM360NG is a MPC5121E based board by ifm ecomatic gmbh.
Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
Sign
mpc5121: add support for PDM360NG board
PDM360NG is a MPC5121E based board by ifm ecomatic gmbh.
Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
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|
| b9947bbb | 24-Apr-2010 |
Anatolij Gustschin <agust@denx.de> |
mpc5121: determine RAM size using get_ram_size()
Configure CONFIG_SYS_MAX_RAM_SIZE address range in
DDR Local Access Window and determine the RAM size.
Fix DDR LAW afterwards using detected RAM size
mpc5121: determine RAM size using get_ram_size()
Configure CONFIG_SYS_MAX_RAM_SIZE address range in
DDR Local Access Window and determine the RAM size.
Fix DDR LAW afterwards using detected RAM size.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
show more ...
|
| 5d937e8b | 24-Apr-2010 |
Anatolij Gustschin <agust@denx.de> |
mpc512x: make MEM IO Control configuration a board config option
Signed-off-by: Anatolij Gustschin <agust@denx.de> |