1 /* 2 * Copyright 2004,2007-2010 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 int checkcpu (void) 39 { 40 sys_info_t sysinfo; 41 uint pvr, svr; 42 uint fam; 43 uint ver; 44 uint major, minor; 45 struct cpu_type *cpu; 46 char buf1[32], buf2[32]; 47 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 48 #ifdef CONFIG_DDR_CLK_FREQ 49 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 50 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 51 #else 52 #ifdef CONFIG_FSL_CORENET 53 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 54 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 55 #else 56 u32 ddr_ratio = 0; 57 #endif /* CONFIG_FSL_CORENET */ 58 #endif /* CONFIG_DDR_CLK_FREQ */ 59 int i; 60 61 svr = get_svr(); 62 major = SVR_MAJ(svr); 63 #ifdef CONFIG_MPC8536 64 major &= 0x7; /* the msb of this nibble is a mfg code */ 65 #endif 66 minor = SVR_MIN(svr); 67 68 if (cpu_numcores() > 1) { 69 #ifndef CONFIG_MP 70 puts("Unicore software on multiprocessor system!!\n" 71 "To enable mutlticore build define CONFIG_MP\n"); 72 #endif 73 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); 74 printf("CPU%d: ", pic->whoami); 75 } else { 76 puts("CPU: "); 77 } 78 79 cpu = gd->cpu; 80 81 puts(cpu->name); 82 if (IS_E_PROCESSOR(svr)) 83 puts("E"); 84 85 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 86 87 pvr = get_pvr(); 88 fam = PVR_FAM(pvr); 89 ver = PVR_VER(pvr); 90 major = PVR_MAJ(pvr); 91 minor = PVR_MIN(pvr); 92 93 printf("Core: "); 94 switch (fam) { 95 case PVR_FAM(PVR_85xx): 96 puts("E500"); 97 break; 98 default: 99 puts("Unknown"); 100 break; 101 } 102 103 if (PVR_MEM(pvr) == 0x03) 104 puts("MC"); 105 106 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 107 108 get_sys_info(&sysinfo); 109 110 puts("Clock Configuration:"); 111 for (i = 0; i < cpu_numcores(); i++) { 112 if (!(i & 3)) 113 printf ("\n "); 114 printf("CPU%d:%-4s MHz, ", 115 i,strmhz(buf1, sysinfo.freqProcessor[i])); 116 } 117 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 118 119 #ifdef CONFIG_FSL_CORENET 120 if (ddr_sync == 1) { 121 printf(" DDR:%-4s MHz (%s MT/s data rate) " 122 "(Synchronous), ", 123 strmhz(buf1, sysinfo.freqDDRBus/2), 124 strmhz(buf2, sysinfo.freqDDRBus)); 125 } else { 126 printf(" DDR:%-4s MHz (%s MT/s data rate) " 127 "(Asynchronous), ", 128 strmhz(buf1, sysinfo.freqDDRBus/2), 129 strmhz(buf2, sysinfo.freqDDRBus)); 130 } 131 #else 132 switch (ddr_ratio) { 133 case 0x0: 134 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 135 strmhz(buf1, sysinfo.freqDDRBus/2), 136 strmhz(buf2, sysinfo.freqDDRBus)); 137 break; 138 case 0x7: 139 printf(" DDR:%-4s MHz (%s MT/s data rate) " 140 "(Synchronous), ", 141 strmhz(buf1, sysinfo.freqDDRBus/2), 142 strmhz(buf2, sysinfo.freqDDRBus)); 143 break; 144 default: 145 printf(" DDR:%-4s MHz (%s MT/s data rate) " 146 "(Asynchronous), ", 147 strmhz(buf1, sysinfo.freqDDRBus/2), 148 strmhz(buf2, sysinfo.freqDDRBus)); 149 break; 150 } 151 #endif 152 153 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 154 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 155 } else { 156 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 157 sysinfo.freqLocalBus); 158 } 159 160 #ifdef CONFIG_CPM2 161 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 162 #endif 163 164 #ifdef CONFIG_QE 165 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 166 #endif 167 168 #ifdef CONFIG_SYS_DPAA_FMAN 169 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 170 printf(" FMAN%d: %s MHz\n", i, 171 strmhz(buf1, sysinfo.freqFMan[i])); 172 } 173 #endif 174 175 #ifdef CONFIG_SYS_DPAA_PME 176 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 177 #endif 178 179 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 180 181 return 0; 182 } 183 184 185 /* ------------------------------------------------------------------------- */ 186 187 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) 188 { 189 /* Everything after the first generation of PQ3 parts has RSTCR */ 190 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 191 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 192 unsigned long val, msr; 193 194 /* 195 * Initiate hard reset in debug control register DBCR0 196 * Make sure MSR[DE] = 1. This only resets the core. 197 */ 198 msr = mfmsr (); 199 msr |= MSR_DE; 200 mtmsr (msr); 201 202 val = mfspr(DBCR0); 203 val |= 0x70000000; 204 mtspr(DBCR0,val); 205 #else 206 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 207 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ 208 udelay(100); 209 #endif 210 211 return 1; 212 } 213 214 215 /* 216 * Get timebase clock frequency 217 */ 218 unsigned long get_tbclk (void) 219 { 220 #ifdef CONFIG_FSL_CORENET 221 return (gd->bus_clk + 8) / 16; 222 #else 223 return (gd->bus_clk + 4UL)/8UL; 224 #endif 225 } 226 227 228 #if defined(CONFIG_WATCHDOG) 229 void 230 watchdog_reset(void) 231 { 232 int re_enable = disable_interrupts(); 233 reset_85xx_watchdog(); 234 if (re_enable) enable_interrupts(); 235 } 236 237 void 238 reset_85xx_watchdog(void) 239 { 240 /* 241 * Clear TSR(WIS) bit by writing 1 242 */ 243 unsigned long val; 244 val = mfspr(SPRN_TSR); 245 val |= TSR_WIS; 246 mtspr(SPRN_TSR, val); 247 } 248 #endif /* CONFIG_WATCHDOG */ 249 250 /* 251 * Configures a UPM. The function requires the respective MxMR to be set 252 * before calling this function. "size" is the number or entries, not a sizeof. 253 */ 254 void upmconfig (uint upm, uint * table, uint size) 255 { 256 int i, mdr, mad, old_mad = 0; 257 volatile u32 *mxmr; 258 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 259 volatile u32 *brp,*orp; 260 volatile u8* dummy = NULL; 261 int upmmask; 262 263 switch (upm) { 264 case UPMA: 265 mxmr = &lbc->mamr; 266 upmmask = BR_MS_UPMA; 267 break; 268 case UPMB: 269 mxmr = &lbc->mbmr; 270 upmmask = BR_MS_UPMB; 271 break; 272 case UPMC: 273 mxmr = &lbc->mcmr; 274 upmmask = BR_MS_UPMC; 275 break; 276 default: 277 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); 278 hang(); 279 } 280 281 /* Find the address for the dummy write transaction */ 282 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; 283 i++, brp += 2, orp += 2) { 284 285 /* Look for a valid BR with selected UPM */ 286 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { 287 dummy = (volatile u8*)(in_be32(brp) & BR_BA); 288 break; 289 } 290 } 291 292 if (i == 8) { 293 printf("Error: %s() could not find matching BR\n", __FUNCTION__); 294 hang(); 295 } 296 297 for (i = 0; i < size; i++) { 298 /* 1 */ 299 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); 300 /* 2 */ 301 out_be32(&lbc->mdr, table[i]); 302 /* 3 */ 303 mdr = in_be32(&lbc->mdr); 304 /* 4 */ 305 *(volatile u8 *)dummy = 0; 306 /* 5 */ 307 do { 308 mad = in_be32(mxmr) & MxMR_MAD_MSK; 309 } while (mad <= old_mad && !(!mad && i == (size-1))); 310 old_mad = mad; 311 } 312 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); 313 } 314 315 /* 316 * Initializes on-chip MMC controllers. 317 * to override, implement board_mmc_init() 318 */ 319 int cpu_mmc_init(bd_t *bis) 320 { 321 #ifdef CONFIG_FSL_ESDHC 322 return fsl_esdhc_mmc_init(bis); 323 #else 324 return 0; 325 #endif 326 } 327