powerpc/mp: add support for discontiguous cores

Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more. We define
CPU_TYPE_ENT

powerpc/mp: add support for discontiguous cores

Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more. We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of /home/wd/git/u-boot/custodians

* 'master' of /home/wd/git/u-boot/custodians:
powerpc/8xxx: Remove dependency on <usb.h>
powerpc/85xx: enable USB2 gadget mode for corenet

Merge branch 'master' of /home/wd/git/u-boot/custodians

* 'master' of /home/wd/git/u-boot/custodians:
powerpc/8xxx: Remove dependency on <usb.h>
powerpc/85xx: enable USB2 gadget mode for corenet ds board
powerpc/85xx: verify the device tree before booting Linux
MPC8xxx: drop redundant boot messages
powerpc/85xx: Fix build failure for P1023RDS
powerpc/p2041rdb: Enable SATA support
powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500
powerpc/85xx: Fix up clock_freq property in CAN node of dts
85xx: enable FDT support for STX SSA board
powerpc/85xx: provide 85xx flush_icache for cmd_cache
powerpc/p2041rdb: Enable backside L2 cache support
powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
powerpc/85xx: Add support for P2041[e] XAUI in SERDES
powerpc/85xx: Rename P2040 id & SERDES to P2041
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access
powerpc/85xx: Fix setting of EPAPR_MAGIC value

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MPC8xxx: drop redundant boot messages

Current code would print RAM size information like this:

DRAM: DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off)

Turn a number of printf()s into debug() to get rid

MPC8xxx: drop redundant boot messages

Current code would print RAM size information like this:

DRAM: DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off)

Turn a number of printf()s into debug() to get rid of the redundant
"DDR: " string like this:

DRAM: 256 MiB (DDR1, 64-bit, CL=2, ECC off)

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500

At some point we broke the detection of e500v1 class cores. Fix that
and simply the code to just utilize PVR_VER() to have a si

powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500

At some point we broke the detection of e500v1 class cores. Fix that
and simply the code to just utilize PVR_VER() to have a single case
statement.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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powerpc/mpc85xx: Add clear_ddr_tlbs function

This is useful when we just want to wipe out the TLBs. There's currently
a function that resets the ddr tlbs to a different value; it is changed to
util

powerpc/mpc85xx: Add clear_ddr_tlbs function

This is useful when we just want to wipe out the TLBs. There's currently
a function that resets the ddr tlbs to a different value; it is changed to
utilize this function. The new function can be used in conjunction with
setup_ddr_tlbs() for a board to temporarily map/unmap the DDR address
range as needed.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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powerpc/mpc8xxx: Enable calculation for fixed DDR chips

We used to have fixed parameters for soldered DDR chips. This patch
introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing

powerpc/mpc8xxx: Enable calculation for fixed DDR chips

We used to have fixed parameters for soldered DDR chips. This patch
introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing
data from DDR chip datasheet, implemneted in board-specific files or header
files.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc/85xx: Change timebase divisor to be defined per processor

Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts. All the PQ3 parts a

powerpc/85xx: Change timebase divisor to be defined per processor

Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts. All the PQ3 parts are
/8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc/85xx: don't init SDRAM when CONFIG_SYS_RAMBOOT

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Conflicts:
drivers/usb/host/ehci-pci.c

Signed-off-by: Wolfgang Denk <wd@denx.de>

powerpc/85xx: Add support for Integrated Flash Controller (IFC)

The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four

powerpc/85xx: Add support for Integrated Flash Controller (IFC)

The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.

Features supported by IFC are,
- Functional muxing of pins between NAND, NOR and GPCM
- Support memory banks of size 64KByte to 4 GBytes
- Write protection capability (only for NAND and NOR)
- Provision of Software Reset
- Flexible Timing programmability for every chip select
- NAND Machine
- x8/ x16 NAND Flash Interface
- SLC and MLC NAND Flash devices support with
configurable
page sizes of upto 4KB
- Internal SRAM of 9KB which is directly mapped and
availble at
boot time for NAND Boot
- Configurable block size
- Boot chip select (CS0) available at system reset
- NOR Machine
- Data bus width of 8/16/32
- Compatible with asynchronous NOR Flash
- Directly memory mapped
- Supports address data multiplexed (ADM) NOR device
- Boot chip select (CS0) available at system reset
- GPCM Machine (NORMAL GPCM Mode)
- Support for x8/16/32 bit device
- Compatible with general purpose addressable device
e.g. SRAM, ROM
- External clock is supported with programmable division
ratio
- GPCM Machine (Generic ASIC Mode)
- Support for x8/16/32 bit device
- Address and Data are shared on I/O bus
- Following Address and Data sequences can be supported
on I/O bus
- 32 bit I/O: AD
- 16 bit I/O: AADD
- 8 bit I/O : AAAADDDD
- Configurable Even/Odd Parity on Address/Data bus
supported

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBC

Future SoC (like the P1010) replace the LBC controller with the new IFC
(Integrated Flash Controller) so ensure we properly protect code that i

powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBC

Future SoC (like the P1010) replace the LBC controller with the new IFC
(Integrated Flash Controller) so ensure we properly protect code that is
related to the LBC.

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN

This config option is for an erratum workaround; rename it to be more
clear. Also, drop it from config files don't need it

85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN

This config option is for an erratum workaround; rename it to be more
clear. Also, drop it from config files don't need it and were
undefining it.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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mpc85xx: rename sdram_init() lbc_sdram_init()

sdram_init() is used to initialize sdram on the lbc. Rename it
accordingly.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kum

mpc85xx: rename sdram_init() lbc_sdram_init()

sdram_init() is used to initialize sdram on the lbc. Rename it
accordingly.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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mpc85xx boards: initdram() cleanup/bugfix

Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I

mpc85xx boards: initdram() cleanup/bugfix

Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts. Most
of the initdram() functions were identical, with 2 common differences:

1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.

2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document. It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled. This seems bad.

The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'next' of ../next

do_reset: unify duplicate prototypes

The duplication of the do_reset prototype has gotten out of hand,
and they're not all in sync. Unify them all in command.h.

Signed-off-by: Mike Frysinger <vapi

do_reset: unify duplicate prototypes

The duplication of the do_reset prototype has gotten out of hand,
and they're not all in sync. Unify them all in command.h.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

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Merge branch 'master' of git://git.denx.de/u-boot-arm

Add memory test feature for mpc85xx POST.

The memory test is performed after DDR initialization when U-boot stills runs
in flash and cache. On recent mpc85xx platforms, the total memory can be more

Add memory test feature for mpc85xx POST.

The memory test is performed after DDR initialization when U-boot stills runs
in flash and cache. On recent mpc85xx platforms, the total memory can be more
than 2GB. To cover whole memory, it needs be mapped 2GB at a time using a
sliding TLB window. After the testing, DDR is remapped with up to 2GB memory
from the lowest address as normal.

If memory test fails, DDR DIMM SPD and DDR controller registers are dumped for
further debugging.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of /home/wd/git/u-boot/master

powerpc/8xxx: share PIC defines among 85xx and 86xx

fixes breakeage introduced by commit
a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query
feature reporting register for num cores on unk

powerpc/8xxx: share PIC defines among 85xx and 86xx

fixes breakeage introduced by commit
a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query
feature reporting register for num cores on unknown cpus"

Reported-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of /home/wd/git/u-boot/master