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bd602528 |
| 09-Jan-2016 |
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
MIPS: reserve space for exception vectors
In order to set own exception handlers, a table with the exception
vectors must be built in DRAM and the CPU EBase register must be
set to the base address
MIPS: reserve space for exception vectors
In order to set own exception handlers, a table with the exception
vectors must be built in DRAM and the CPU EBase register must be
set to the base address of this table.
Reserve the space above the stack and use gd->irq_sp as storage
for the exception base address.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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