| 01911422 | 12-Sep-2012 |
Marek Vasut <marex@denx.de> |
serial: mips: Implement CONFIG_SERIAL_MULTI into asc serial driver
Implement support for CONFIG_SERIAL_MULTI into asc serial driver.
This driver was so far only usable directly, but this patch also
serial: mips: Implement CONFIG_SERIAL_MULTI into asc serial driver
Implement support for CONFIG_SERIAL_MULTI into asc serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the asc driver. Also, add a weak implementation
of default_serial_console() returning this driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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| 6cb461b4 | 02-Apr-2012 |
Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> |
MIPS: fix endianess handling
Make endianess of target CPU configurable. Use the new config
option for dbau1550_el and pb1000 boards.
Adapt linking of standalone applications to pass through
endiane
MIPS: fix endianess handling
Make endianess of target CPU configurable. Use the new config
option for dbau1550_el and pb1000 boards.
Adapt linking of standalone applications to pass through
endianess options to LD.
Build tested with:
- ELDK 4 mips_4KC- and mips4KCle
- Sourcery CodeBench Lite 2011.03-93
With this patch all 26 MIPS boards can be compiled now in one step by
running "MAKEALL -a mips".
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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| ab2a98b1 | 27-Jul-2011 |
Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> |
MIPS: make cache operation mode configurable
Currently the cache operation mode is hard-coded to
CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs
which operate at a different mo
MIPS: make cache operation mode configurable
Currently the cache operation mode is hard-coded to
CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs
which operate at a different mode.
This patch makes the cache operation mode configurable via board config.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
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| 68cebb80 | 06-May-2011 |
Shinya Kuribayashi <skuribay@pobox.com> |
MIPS: Move timer code to arch/mips/cpu/$(CPU)/
Current timer routines (arch/mips/lib/timer.c) are implemented assuming
that MIPS32 coprocessor (CP0) resources, Counter and Compare registers
in this
MIPS: Move timer code to arch/mips/cpu/$(CPU)/
Current timer routines (arch/mips/lib/timer.c) are implemented assuming
that MIPS32 coprocessor (CP0) resources, Counter and Compare registers
in this case, are available. But this doesn't always work.
We need to make sure that all MIPS-based systems don't necessarily use
CP0 counter/compare registers as time keeping resources. And some MIPS
variant processors might come with different hardware specs with genuine
MIPS32 CP0 registers.
With this change, each $(CPU)/ directory can have its own timer code.
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
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| 7aa1f198 | 06-May-2011 |
Shinya Kuribayashi <skuribay@pobox.com> |
MIPS: Coding style cleanups on common assembly files
Fix style issues and alignments globally. No logical changes.
- Replace C comments with AS line comments where possible
- Use ifndef where possi
MIPS: Coding style cleanups on common assembly files
Fix style issues and alignments globally. No logical changes.
- Replace C comments with AS line comments where possible
- Use ifndef where possible, rather than if !defined for simplicity
- An instruction executed in a delay slot is now indicated by a leading
space, not by C comment
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
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