Merge git://git.denx.de/u-boot-uniphier

- add {ofnode,dev}_read_resource_byname
- provide DT probe hook to Denali NAND driver
- update clk/reset driver
- update DT
- misc cleanups

ARM: uniphier: move PLLCTRL register macros to each SoC .c file

The new SoC PXs3 changed the address of PLL, but still uses the
same PLL name. We can not define SC_*PLLCTRL in the common header.
Mo

ARM: uniphier: move PLLCTRL register macros to each SoC .c file

The new SoC PXs3 changed the address of PLL, but still uses the
same PLL name. We can not define SC_*PLLCTRL in the common header.
Move them to per-SoC .c file. Also, fix some PLL comments.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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ARM: uniphier: replace <common.h> with <linux/delay.h> in pll settings

The #include <common.h> was added for mdelay(). Later, the declaration
of mdelay was moved to <linux/delay.h> by commit 5bc516

ARM: uniphier: replace <common.h> with <linux/delay.h> in pll settings

The #include <common.h> was added for mdelay(). Later, the declaration
of mdelay was moved to <linux/delay.h> by commit 5bc516ed661a ("delay:
collect {m, n, u}delay declarations to include/linux/delay.h").

There is no need to include <common.h> now.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge branch 'master' of git://git.denx.de/u-boot-uniphier

- Enable eMMC driver for LD11/LD20 SoCs
- Refactoring of SoC init code
- Bug fix of pinctrl driver

ARM: uniphier: remove unneeded argument of uniphier_ld20_pll_init()

At first, we thought the LD20 PLL setting would be board dependent,
but this argument turned out unneeded after all.

Signed-off-b

ARM: uniphier: remove unneeded argument of uniphier_ld20_pll_init()

At first, we thought the LD20 PLL setting would be board dependent,
but this argument turned out unneeded after all.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge branch 'master' of git://git.denx.de/u-boot-uniphier

ARM: uniphier: enable SSC for more PLLs for LD20 SoC

For Electro-Magnetic Compatibility.

Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent.

Signed-off-by: Masahiro Yamada <yamada.ma

ARM: uniphier: enable SSC for more PLLs for LD20 SoC

For Electro-Magnetic Compatibility.

Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge branch 'master' of git://git.denx.de/u-boot-uniphier

ARM: uniphier: add PLL init code for LD20 SoC

Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper. Split the common code into pll-base-ld20.c for easier
re-use.

Signed-off-by: M

ARM: uniphier: add PLL init code for LD20 SoC

Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper. Split the common code into pll-base-ld20.c for easier
re-use.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...