Merge branch 'master' of git://git.denx.de/u-boot-socfpga

arm: socfpga: Restructure reset manager driver

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.

Signed-off-by: Ley Foon Tan <ley.foon.t

arm: socfpga: Restructure reset manager driver

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

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Merge git://git.denx.de/u-boot-socfpga

arm: socfpga: Assure ISWGRP 0 and 1 are inited

This fix makes sure that the ISWGRP0 and ISWGRP1 registers are
correctly inited. In case those registers are not initialized,
it is not possible to acc

arm: socfpga: Assure ISWGRP 0 and 1 are inited

This fix makes sure that the ISWGRP0 and ISWGRP1 registers are
correctly inited. In case those registers are not initialized,
it is not possible to access the registers synthesised in the
FPGA through the bridges. Any such access produces data abort.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

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arm: socfpga: reset: Add function to reset add peripherals

Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.

Signed-off-by: Marek Vasut <

arm: socfpga: reset: Add function to reset add peripherals

Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Repair bridge reset handling

The current bridge reset code, which de-asserted the bridge reset,
was activelly polling whether the FPGA is programmed and ready and
in case it was

arm: socfpga: reset: Repair bridge reset handling

The current bridge reset code, which de-asserted the bridge reset,
was activelly polling whether the FPGA is programmed and ready and
in case it was (!), the code called hang(). This makes no sense at
all. Repair it such that the code instead checks whether the FPGA
is programmed, but without any polling involved, and only if it is
programmed, it de-asserts the reset.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Replace ad-hoc reset functions

Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function,

arm: socfpga: reset: Replace ad-hoc reset functions

Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function, socfpga_per_reset(), with necessary parameters.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Implement unified function to toggle reset

Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
man

arm: socfpga: reset: Implement unified function to toggle reset

Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
manner. Use this function throughout reset manager.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Start reworking the SoCFPGA reset manager

Implement macro SOCFPGA_RESET(name), which produces an abstract
reset number. Implement macros which allow extracting the reset
offset

arm: socfpga: reset: Start reworking the SoCFPGA reset manager

Implement macro SOCFPGA_RESET(name), which produces an abstract
reset number. Implement macros which allow extracting the reset
offset in permodrstN register and which permodrstN register the
reset is located in from this abstract reset number. Use these
macros throughout the reset manager.

Signed-off-by: Marek Vasut <marex@denx.de>

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ARM: socfpga: move SoC sources to mach-socfpga

Our recent trend is to collect SoC files into arch/arm/mach-(SOC).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>