| #
0e00a84c |
| 04-Mar-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
UPSTREAM: libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>
Thomas reported U-Boot failed to build host tools if libfdt-devel package is installed because tools include libfdt header
UPSTREAM: libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>
Thomas reported U-Boot failed to build host tools if libfdt-devel package is installed because tools include libfdt headers from /usr/include/ instead of using internal ones.
This commit moves the header code: include/libfdt.h -> include/linux/libfdt.h include/libfdt_env.h -> include/linux/libfdt_env.h
and replaces include directives: #include <libfdt.h> -> #include <linux/libfdt.h> #include <libfdt_env.h> -> #include <linux/libfdt_env.h>
Change-Id: I6c0f7e50e8b571106627f25ddac008a62bd2994e Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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| #
753a4dde |
| 18-May-2017 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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| #
d1c559af |
| 25-Apr-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: Restructure misc driver
Restructure misc driver in the preparation to support A10. Move the Gen5 specific code to gen5 file.
Change all uint32_t_to u32.
Signed-off-by: Ley Foon Tan <
arm: socfpga: Restructure misc driver
Restructure misc driver in the preparation to support A10. Move the Gen5 specific code to gen5 file.
Change all uint32_t_to u32.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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| #
3450a859 |
| 24-Oct-2016 |
Vagrant Cascadian <vagrant@debian.org> |
Fix spelling of "resetting".
Cover-Letter: Fixes several spelling errors for the words "resetting", "extended", "occur", and "multiple".
Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Revi
Fix spelling of "resetting".
Cover-Letter: Fixes several spelling errors for the words "resetting", "extended", "occur", and "multiple".
Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
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| #
52b1eaf9 |
| 17-May-2016 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
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| #
15e8cb70 |
| 07-May-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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| #
5289c5fa |
| 06-May-2016 |
Anatolij Gustschin <agust@denx.de> |
socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled
Building without ethernet driver doesn't work. Fix it.
Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
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| #
9dbdc6eb |
| 10-Apr-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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| #
dafd5792 |
| 19-Mar-2016 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Nuke useless include
The dwmmc.h include was forgotten during the migration of dwmmc probing to DM. Since the shiny DM is in place now, remove this relic of the past.
Signed-off-by: M
arm: socfpga: Nuke useless include
The dwmmc.h include was forgotten during the migration of dwmmc probing to DM. Since the shiny DM is in place now, remove this relic of the past.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
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| #
5f79d008 |
| 21-Mar-2016 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Handle phy-mode OF property for GMACs
Thus far, the socfpga init code had hard-coded the configuration of the ethernet PHY interface to RGMII in the ethernet registers in sysmgr space,
arm: socfpga: Handle phy-mode OF property for GMACs
Thus far, the socfpga init code had hard-coded the configuration of the ethernet PHY interface to RGMII in the ethernet registers in sysmgr space, so PHYs connected in another modes did not work.
This patch fixes support for configurations where the ethernet PHYs are connected over MII/GMII/RMII interfaces by parsing the phy-mode OF property of the GMACs and configuring the ethernet registers in sysmgr space accordingly.
Signed-off-by: Marek Vasut <marex@denx.de> Reported-by: Denis Bakhvalov <denis.bakhvalov@nokia.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
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| #
cdb714d7 |
| 24-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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| #
e6e34ca3 |
| 11-Feb-2016 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Fix ethernet reset handling
The following patch caused cpu_eth_init() to not be called anymore for DM-capable boards:
commit c32a6fd07b1839e4a45729587ebc8e1c55601a4d Date: Sun Jan 1
arm: socfpga: Fix ethernet reset handling
The following patch caused cpu_eth_init() to not be called anymore for DM-capable boards:
commit c32a6fd07b1839e4a45729587ebc8e1c55601a4d Date: Sun Jan 17 14:51:56 2016 -0700 net: Don't call board/cpu_eth_init() with driver model
This breaks ethernet on SoCFPGA, since we use that function to un-reset the ethernet blocks. Invoke the ethernet reset function from arch_misc_init() instead to fix the breakage.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Denis Bakhvalov <denis.bakhvalov@nokia.com>
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| #
40253dd1 |
| 24-Dec-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-socfpga
Conflicts: include/configs/axs101.h
Signed-off-by: Tom Rini <trini@konsulko.com>
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| #
8f7ed08e |
| 20-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Unreset NAND in U-Boot
Make sure the NAND reset is not asserted in full U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Li
arm: socfpga: Unreset NAND in U-Boot
Make sure the NAND reset is not asserted in full U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
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| #
07806977 |
| 20-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Actually enable L2 cache
The L2 cache was never enabled in the v7_outer_cache_enable(), fix this and enable the L2 cache.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <d
arm: socfpga: Actually enable L2 cache
The L2 cache was never enabled in the v7_outer_cache_enable(), fix this and enable the L2 cache.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
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| #
1c75596e |
| 30-Nov-2015 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Remove cpu_mmc_init()
This function triggers the registration of the dwmmc driver on SoCFPGA, but this is not needed in case the driver is correctly probed from DT.
Signed-off-by: Mar
arm: socfpga: Remove cpu_mmc_init()
This function triggers the registration of the dwmmc driver on SoCFPGA, but this is not needed in case the driver is correctly probed from DT.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
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| #
a69fdc77 |
| 23-Oct-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
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| #
ac6a5321 |
| 17-Oct-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-socfpga
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| #
8d8e13e1 |
| 15-Oct-2015 |
Dinh Nguyen <dinguyen@opensource.altera.com> |
arm: socfpga: enable data/inst prefetch and shared override in the L2
Update the L2 AUX CTRL settings for the SoCFPGA.
Enabling D and I prefetch bits helps improve SDRAM performance on the platform
arm: socfpga: enable data/inst prefetch and shared override in the L2
Update the L2 AUX CTRL settings for the SoCFPGA.
Enabling D and I prefetch bits helps improve SDRAM performance on the platform.
Also, we need to enable bit 22 of the L2. By not having bit 22 set in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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| #
a6003397 |
| 07-Sep-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-socfpga
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| #
129adf5b |
| 25-Jul-2015 |
Marek Vasut <marex@denx.de> |
mmc: dw_mmc: Probe the MMC from OF
Rework the driver to probe the MMC controller from Device Tree and make it mandatory. There is no longer support for probing from the ancient qts-generated header
mmc: dw_mmc: Probe the MMC from OF
Rework the driver to probe the MMC controller from Device Tree and make it mandatory. There is no longer support for probing from the ancient qts-generated header files.
This patch now also removes previous temporary workaround.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
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| #
bd48c061 |
| 01-Aug-2015 |
Dinh Nguyen <dinguyen@opensource.altera.com> |
arm: socfpga: misc: Add support for printing FPGA type
Add code which uses the new functions for obtaining FPGA ID from the scan manager. This new code prints the FPGA model attached to the SoCFPGA
arm: socfpga: misc: Add support for printing FPGA type
Add code which uses the new functions for obtaining FPGA ID from the scan manager. This new code prints the FPGA model attached to the SoCFPGA during boot and sets environment variable "fpgatype", which can be used to determine the FPGA model in U-Boot scripts.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de>
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| #
03439e40 |
| 03-Aug-2015 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Add temporary workaround for missing SD/MMC patches
Add a small workaround into the platform code which forces the SDMMC into 8-bit mode (the default configuration for all socfpga plat
arm: socfpga: Add temporary workaround for missing SD/MMC patches
Add a small workaround into the platform code which forces the SDMMC into 8-bit mode (the default configuration for all socfpga platforms) to work around breakage caused by missing patches in mainline which switch the probing of SD/MMC to OF instead of static configuraiton.
The patches will hit mainline after the SPL series, so to avoid build issues, add this small temporary workaround.
Signed-off-by: Marek Vasut <marex@denx.de>
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| #
6ab00db2 |
| 25-Jul-2015 |
Marek Vasut <marex@denx.de> |
arm: socfpga: misc: Reset ethernet from OF
Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc hardcoded values in the U-Boot code. Since we don't have a proper reset framework
arm: socfpga: misc: Reset ethernet from OF
Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc hardcoded values in the U-Boot code. Since we don't have a proper reset framework in place yet, we have to do this slightly ad-hoc parsing of the OF tree instead.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
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| #
e14d3f79 |
| 25-Jul-2015 |
Marek Vasut <marex@denx.de> |
arm: socfpga: misc: Probe ethernet GMAC from OF
The GMAC can now be probed from OF, so enable DM ethernet and remove the old ad-hoc designware_initialize() invocation.
Signed-off-by: Marek Vasut <m
arm: socfpga: misc: Probe ethernet GMAC from OF
The GMAC can now be probed from OF, so enable DM ethernet and remove the old ad-hoc designware_initialize() invocation.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
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