| 2283284b | 23-Mar-2016 |
Nishanth Menon <nm@ti.com> |
ARM: keystone2: Add missing privilege ID settings
Add missing Privilege ID settings for KS2 SoCs.
Based on: K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013) http://www.ti.com/lit/
ARM: keystone2: Add missing privilege ID settings
Add missing Privilege ID settings for KS2 SoCs.
Based on: K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013) http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99) K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015) http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71) K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015) http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75) K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016) http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)
Overall mapping: -------+-----------+-----------+-----------+--------- PrivID | KS2H/K | K2L | K2E | K2G -------+-----------+-----------+-----------+--------- 0 | C66x 0 | C66x 0 | C66x 0 | C66x 0 1 | C66x 1 | C66x 1 | Reserved | ARM 2 | C66x 2 | C66x 2 | Reserved | ICSS0 3 | C66x 3 | C66x 3 | Reserved | ICSS1 4 | C66x 4 | Reserved | Reserved | NETCP 5 | C66x 5 | Reserved | Reserved | CPIE 6 | C66x 6 | Reserved | Reserved | USB 7 | C66x 7 | Reserved | Reserved | Reserved 8 | ARM | ARM | ARM | MLB 9 | NetCP | NetCP | NetCP | PMMC 10 | QM_PDSP | QM_PDSP | QM_PDSP | DSS 11 | PCIe_0 | PCIe_0 | PCIe_0 | MMC 12 | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP 13 | Reserved | Reserved | PCIe_1 | Reserved 14 | HyperLink | PCIe_1 | HyperLink | Reserved 15 | Reserved | Reserved | TSIP | Reserved -------+-----------+-----------+-----------+---------
NOTE: Few of these might have default configurations, however, since most are software configurable, it is better to explicitly configure the system to have a known default state.
Without programming these, we end up seeing lack of coherency on certain peripherals resulting in inexplicable failures (such as USB peripheral's DMA data not appearing on ARM etc and weird workarounds being done by drivers including cache flushes which tend to have system wide performance impact).
By marking these segments as shared, we also ensure SoC wide coherency is enabled.
Reported-by: Bin Liu <b-liu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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| 705c506e | 15-Mar-2016 |
Nishanth Menon <nm@ti.com> |
ARM: keystone2: Convert BOOT_SET_BITFIELD into static inline function
Fix up BOOT_SET_BITFIELD to be a static inline function to be readable with the same functionality.
Reported-by: Tom Rini <trin
ARM: keystone2: Convert BOOT_SET_BITFIELD into static inline function
Fix up BOOT_SET_BITFIELD to be a static inline function to be readable with the same functionality.
Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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| f84e8e5b | 15-Mar-2016 |
Nishanth Menon <nm@ti.com> |
ARM: keystone2: Convert BOOT_READ_BITFIELD into static inline function
BOOT_READ_BITFIELD can easily be a static inline function and be a little more readable with the same functionality.
Reported-
ARM: keystone2: Convert BOOT_READ_BITFIELD into static inline function
BOOT_READ_BITFIELD can easily be a static inline function and be a little more readable with the same functionality.
Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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| 8efc2437 | 04-Mar-2016 |
Vitaly Andrianov <vitalya@ti.com> |
ARM: keystone2: use detected ddr3a size
Because KS2 u-boot works in 32 bit address space the existing ram_size global data field cannot be used. The maximum, which the get_ram_size() can detect is 2
ARM: keystone2: use detected ddr3a size
Because KS2 u-boot works in 32 bit address space the existing ram_size global data field cannot be used. The maximum, which the get_ram_size() can detect is 2GB only. The ft_board_setup() needs the actual ddr3 size to fix up dtb.
This commit introduces the ddr3_get_size() which uses SPD data to calculate the ddr3 size. This function replaces the "ddr3_size" environment variable, which was used to get the SODIMM size.
For platforms, which don't have SODIMM with SPD and ddr3 is populated to a board a simple ddr3_get_size function that returns ddr3 size has to be implemented. See hardware-k2l.h
Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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| ef76ebb1 | 04-Mar-2016 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: keystone2: K2G: Add support for different arm/device speeds
The maximum device and arm speeds can be determined by reading EFUSE_BOOTROM register. As there is already a framework for reading th
ARM: keystone2: K2G: Add support for different arm/device speeds
The maximum device and arm speeds can be determined by reading EFUSE_BOOTROM register. As there is already a framework for reading this register, adding support for all possible speeds on k2g devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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| 5cd1f6bd | 04-Mar-2016 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: keystone2: Allow for board specific speed definitions
Its not compulsory that speed definition should be same on EFUSE_BOOTROM register for all keystone 2 devices. So, allow for board specific
ARM: keystone2: Allow for board specific speed definitions
Its not compulsory that speed definition should be same on EFUSE_BOOTROM register for all keystone 2 devices. So, allow for board specific speed definitions.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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| f2a8279e | 04-Mar-2016 |
Suman Anna <s-anna@ti.com> |
ARM: keystone2: K2G: power-off DSP during boot
The DSPs are powered on by default upon a Power ON reset, and they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E during the boot in u-boo
ARM: keystone2: K2G: power-off DSP during boot
The DSPs are powered on by default upon a Power ON reset, and they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E during the boot in u-boot. This is not functional on K2G though. Extend the existing DSP power-off support to the only DSP present on K2G. Do note that the PSC clock domain module id for DSP on K2G differs from that of previous Keystone2 SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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| ec00b2e3 | 25-Feb-2016 |
Nishanth Menon <nm@ti.com> |
ARM: keystone2: psc: introduce function to hold and release module in reset.
These are useful for modules that need to be held in reset and are enabled for data to be loaded on to them. Typically th
ARM: keystone2: psc: introduce function to hold and release module in reset.
These are useful for modules that need to be held in reset and are enabled for data to be loaded on to them. Typically these are microcontrollers or other processing entities in the system.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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| cddb3300 | 19-Sep-2015 |
Vitaly Andrianov <vitalya@ti.com> |
ARM: k2g: update keystone nav rx queue numbers
update K2G nav rx queue number
Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Loke
ARM: k2g: update keystone nav rx queue numbers
update K2G nav rx queue number
Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| 11d8222a | 19-Sep-2015 |
Vitaly Andrianov <vitalya@ti.com> |
ARM: k2g: Correct base addresses
Coreect base addresses for SPI, Queue Manager, Ethernet, GPIO, and MSMC segments.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <loke
ARM: k2g: Correct base addresses
Coreect base addresses for SPI, Queue Manager, Ethernet, GPIO, and MSMC segments.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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