| 9319a756 | 23-Mar-2017 |
Wenyou Yang <wenyou.yang@atmel.com> |
pinctrl: at91: add pinctrl driver
AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.
Each SoC w
pinctrl: at91: add pinctrl driver
AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.
Each SoC will have to describe the its limitation and pin
configuration via device tree. This will allow to do not need
to touch the C code when adding new SoC if the IP version is
supported.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| 46ed9381 | 20-Jul-2016 |
Wenyou Yang <wenyou.yang@atmel.com> |
gpio: atmel_pio4: Move PIO4 definitions to head file
In order to make these PIO4 definitions shared with AT91 PIO4
pinctrl driver, move them from the existing gpio driver to the
head file, and rephr
gpio: atmel_pio4: Move PIO4 definitions to head file
In order to make these PIO4 definitions shared with AT91 PIO4
pinctrl driver, move them from the existing gpio driver to the
head file, and rephrase them.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| 41bf25c2 | 03-Feb-2016 |
Wenyou Yang <wenyou.yang@atmel.com> |
ARM: at91: clock: add a new file to handle clock
To reduce the duplicated code, add a new file to accommodate
the peripheral's and system's clock handle code, shared with
the SoCs with different ARM
ARM: at91: clock: add a new file to handle clock
To reduce the duplicated code, add a new file to accommodate
the peripheral's and system's clock handle code, shared with
the SoCs with different ARM core.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
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| c2ad76c4 | 01-Feb-2016 |
Wenyou Yang <wenyou.yang@atmel.com> |
arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization
The DDR3-SDRAM initialization sequence is implemented in
accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section
described in the
arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization
The DDR3-SDRAM initialization sequence is implemented in
accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section
described in the SAMA5D2 datasheet.
Add registers and definitions of mpddrc controller, which is used
to support DDR3 devices.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
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