| 6f22b15e | 17-Jun-2022 |
Jianqun Xu <jay.xu@rock-chips.com> |
rockchip: rk3588: fix aclk_vop_root_sel to 3bit width
Reference to trm the aclk_vop_root_sel has 3bit width.
Change-Id: I2f87e427446f59d408dcf89ed175ddb95ae0a8fb
Signed-off-by: Jianqun Xu <jay.xu@r
rockchip: rk3588: fix aclk_vop_root_sel to 3bit width
Reference to trm the aclk_vop_root_sel has 3bit width.
Change-Id: I2f87e427446f59d408dcf89ed175ddb95ae0a8fb
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
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|
| 76534374 | 15-Jun-2022 |
Ziyuan Xu <xzy.xu@rock-chips.com> |
clk: rockchip: rv1106: change APLL_HZ to 1.1G
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Ia017309069dd9ff0d3ca6e1dd0d66217a27e09fb |
| 9d10124a | 11-May-2022 |
Joseph Chen <chenjh@rock-chips.com> |
rockchip: param: Fix disable uart when no serial atag
rk3036, rk312x doesn't have enough sram size to pass
the serial atag.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I490018f522
rockchip: param: Fix disable uart when no serial atag
rk3036, rk312x doesn't have enough sram size to pass
the serial atag.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I490018f522da1e7acefa6729ed84c3ffb9b4947a
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|
| 056cae5c | 13-Apr-2022 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3588: change cpul clock source to pvtpll
Change-Id: I4ab6d15c05b4cb805b60125cb5bb7e7d2e65d6e5
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> |
| 3a7297c2 | 21-Apr-2022 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rk3588: Init the PPLL to 1.1G
The pcie2 combophy clk output will have better quality in this setting.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I9e312123a51d7f34c6c22780
clk: rk3588: Init the PPLL to 1.1G
The pcie2 combophy clk output will have better quality in this setting.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I9e312123a51d7f34c6c22780148f63d14c147442
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|
| 5029b474 | 18-Apr-2022 |
Joseph Chen <chenjh@rock-chips.com> |
rockchip: Introduce CONFIG_ROCKCHIP_BOOTDEV
Usually we get boot device from preloader or scan list on the
board with single storage. While for the multiple storage, we
introduce this option to deter
rockchip: Introduce CONFIG_ROCKCHIP_BOOTDEV
Usually we get boot device from preloader or scan list on the
board with single storage. While for the multiple storage, we
introduce this option to determine which we really want to be
the boot device, which contains kernel, rootfs and etc.
When this option is NULL string, we fall through to get boot
device from preloader or scan list.
Example: CONFIG_ROCKCHIP_BOOTDEV="nvme 0".
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I734dc0ab2bb7104a1584cbddc15620c890970223
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| b81ef8b2 | 15-Apr-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: add dclk_decom
Change-Id: Ied47331ddb33fc73491875743667f1e4afcb8eb2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| b4fd97a6 | 29-Mar-2022 |
Joseph Chen <chenjh@rock-chips.com> |
rockchip: vendor: Add hdcp data handle
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I9ca8b8b4933932bfb4c41893a242ecb9ed0b8fb7 |
| 37e50c68 | 29-Mar-2022 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
rockchip: vendor storage: add HDCP_14_HDMIRX_ID
Modify SENSOR_CALIBRATION_ID from 13 to 14 and add
SENSOR_CALIBRATION_ID.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ie7cccc7
rockchip: vendor storage: add HDCP_14_HDMIRX_ID
Modify SENSOR_CALIBRATION_ID from 13 to 14 and add
SENSOR_CALIBRATION_ID.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ie7cccc76627db0a7f8006a1b767df8efad414c63
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| 32914815 | 26-Mar-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: add grf clk
add grf clk for emmc\sdio\sdmmc sample and drv.
Change-Id: I35c1c7aa0387e3d62fed37264a23a230e45e7194
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 75bf999a | 22-Mar-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: add core div setting
fix kernel clk summary:
pll_apll 1 1 0 816000000
apll 1 1 0 816
clk: rockchip: rv1106: add core div setting
fix kernel clk summary:
pll_apll 1 1 0 816000000
apll 1 1 0 816000000
armclk 1 1 0 408000000
Change-Id: I4fc0a20d36c6768b4dd26f61ef74c28d2b0c97ff
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| 89cc3f4d | 10-Aug-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: px30: add otp clk and support px30s
Change-Id: I4e16a4e28a25ce3897a368a35da560faf8264640
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> |
| 7d793375 | 02-Mar-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: support rockchip image tiny
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I59bc654ea6ebd3a9c7e847b99433c713b850ed6e |
| 79475ff5 | 02-Mar-2022 |
David Wu <david.wu@rock-chips.com> |
include: arch-rockchip: rv1106: Add grf struct
Change-Id: I165996d86bfe12ce58799f6a31d8e00cf8a65971
Signed-off-by: David Wu <david.wu@rock-chips.com> |
| 04e2aa7f | 11-Jan-2022 |
Joseph Chen <chenjh@rock-chips.com> |
rockchip: Add rv1106 support
Sync dts from develop-5.10:
(465c41218f8e pinctrl: rockchip: build depends on CPU config).
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Jason Zhu <
rockchip: Add rv1106 support
Sync dts from develop-5.10:
(465c41218f8e pinctrl: rockchip: build depends on CPU config).
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I72e5b5172bfdc1686403a606e0f3559f71467ecf
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| a5a5ddb9 | 18-Jan-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: Add clock controller for the RV1106
Add the clock tree definition for the new RV1106 SoC.
Change-Id: Ifc9778851608337fda121297cc0d1200706cf72b
Signed-off-by: Elaine Zhang <zhangqing@
clk: rockchip: Add clock controller for the RV1106
Add the clock tree definition for the new RV1106 SoC.
Change-Id: Ifc9778851608337fda121297cc0d1200706cf72b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| b6d6b016 | 24-Feb-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
clk: rockchip: rk3588: support setting dp aux channel clk
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I65954d0805ce51c042dd5ca469781fb55ab1bccc |
| d8e6f8d0 | 31-Dec-2021 |
Joseph Chen <chenjh@rock-chips.com> |
rockchip: ram: support extend ram top
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I1d8a5e9440071194a1c438345c08e7e2c4d0d3dc |
| 3ec6da6d | 16-Feb-2022 |
Joseph Chen <chenjh@rock-chips.com> |
rockchip: atags: Add boot param
The boot param is configured in loader ini file
and passed from ddr bin.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic0e1492aaf57e142e0b0ea7991d6b
rockchip: atags: Add boot param
The boot param is configured in loader ini file
and passed from ddr bin.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic0e1492aaf57e142e0b0ea7991d6bf2304c22152
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| 39cedad5 | 21-Feb-2022 |
Joseph Chen <chenjh@rock-chips.com> |
include: global_data: fix compiler error if disable I/D cache
common/spl/spl.c: In function ‘spl_dcache_enable’:
common/spl/spl.c:266:10: error: ‘volatile struct arch_global_data’ has no member name
include: global_data: fix compiler error if disable I/D cache
common/spl/spl.c: In function ‘spl_dcache_enable’:
common/spl/spl.c:266:10: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_size’
gd->arch.tlb_size = PGTABLE_SIZE;
^
common/spl/spl.c:267:10: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_addr’
gd->arch.tlb_addr = (ulong)memalign(SZ_16K, ALIGN(PGTABLE_SIZE, SZ_4K));
^
common/spl/spl.c:268:15: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_addr’
if (!gd->arch.tlb_addr) {
^
CC tpl/arch/arm/lib/spl.o
CC spl/common/fdt_support.o
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ifd6cf6cd8309867e1b51ce5c1f32dcfdb600c515
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| da48e024 | 22-Jan-2022 |
Algea Cao <algea.cao@rock-chips.com> |
clk: rockchip: rk3588: Support hdmiphy pll
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I4fa787ed2b6057579985ab8469adef888eee1ee7 |
| 25a706d2 | 12-Jan-2022 |
Joseph Chen <chenjh@rock-chips.com> |
rockchip: fit: make resource code can be disabled
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ia7f9721efb45d95ea46a1e16c6259249a1c61a09 |
| 1a4d12c4 | 17-Jan-2022 |
Joseph Chen <chenjh@rock-chips.com> |
rockchip: param: add param_simple_parse_ddr_mem()
Active if no define CONFIG_BIDRAM. Mainly used on critical
size platform.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ib361ecde6d
rockchip: param: add param_simple_parse_ddr_mem()
Active if no define CONFIG_BIDRAM. Mainly used on critical
size platform.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ib361ecde6db54c9a0b534ef62a634b0e4155bc28
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|
| 01dba696 | 26-Oct-2021 |
Liang Chen <cl@rock-chips.com> |
rockchip: add soc version for px30s
Change-Id: Ia567a7be7c20d2f399a0124f12afcb822150cccf
Signed-off-by: Liang Chen <cl@rock-chips.com> |
| 045d3eaa | 31-Dec-2021 |
Joseph Chen <chenjh@rock-chips.com> |
rockchip: param: move atags parse code to param.c
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I5a832267824debbe31a8e8dd40607fd8b30dd7f4 |