rockchip: pinctrl: rk3399: add GMAC (RGMII only) support

To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration. This commit

rockchip: pinctrl: rk3399: add GMAC (RGMII only) support

To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration. This commit
adds the pinctrl support for GMAC in RGMII signalling mode:
* adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
* adds the required defines (in the GRF support) for configuring the
GPIOC pins for RGMII
* configures the RGMII pins (in GPIOC) when requested via pinctrl

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>

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rockchip: video: Split out HDMI controller code

Designware HDMI controller and phy are used in other SoCs as well. Split
out platform independent code.

DW HDMI has 8 bit registers but they can be r

rockchip: video: Split out HDMI controller code

Designware HDMI controller and phy are used in other SoCs as well. Split
out platform independent code.

DW HDMI has 8 bit registers but they can be represented as 32 bit
registers as well. Add support to select access mode.

EDID reading code use reading by blocks which is not supported by other
SoCs in general. Make it more general using byte by byte approach, which
is also used in Linux driver.

Finally, not all DW HDMI controllers are accompanied with DW HDMI phy.
Support custom phys by making controller code independent from phy code.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Tested-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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rockchip: clk: rk3188: Allow configuration of the armclk

The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
startup take a lot of time. We therefore want to at least move to

rockchip: clk: rk3188: Allow configuration of the armclk

The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
startup take a lot of time. We therefore want to at least move to the safe
600MHz value we can use with default pmic settings.
This is also the freqency the proprietary sdram-init leaves the cpu at.

For boards that have pmic control later in u-boot, we also add the option
to set the maximum frequency of 1.6GHz, if they so desire.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>

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rockchip: spl: RK3399: use boot0 hook to create space for SPL magic

The SPL binary needs to be prefixed with the boot magic ('RK33' for
the RK3399) on the Rockchip platform and starts execution of t

rockchip: spl: RK3399: use boot0 hook to create space for SPL magic

The SPL binary needs to be prefixed with the boot magic ('RK33' for
the RK3399) on the Rockchip platform and starts execution of the
instruction word following immediately after this boot magic.

This poses a challenge for AArch64 (ARMv8) binaries, as the .text
section would need to start on the odd address, violating natural
alignment (and potentially triggering a fault for any code that
tries to access 64bit values embedded in the .text section).

A quick and easy fix is to have the .text section include the 'RK33'
magic and pad it with a boot0 hook to insert 4 bytes of padding at the
start of the section (with the intention of having mkimage overwrite
this padding with the appropriate boot magic). This avoids having to
modify the linker scripts or more complex logic in mkimage.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>

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Merge git://git.denx.de/u-boot-tegra

Merge git://git.denx.de/u-boot-fsl-qoriq

mmc: tegra: allow disabling external clock loopback

Introduce CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK to disable the external clock
loopback and use the internal one on SDMMC3 as per the SDMMC_VEND

mmc: tegra: allow disabling external clock loopback

Introduce CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK to disable the external clock
loopback and use the internal one on SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0
register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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arvm8: pcie-layerscape: Define stream-ids for Layerscape Chassis-2

Layerscape Chassis-2 have PCIe device, some platform devices and
DPAA1 devices which will use stream-ids for iommu level isolation

arvm8: pcie-layerscape: Define stream-ids for Layerscape Chassis-2

Layerscape Chassis-2 have PCIe device, some platform devices and
DPAA1 devices which will use stream-ids for iommu level isolation
as they are behind SMMU.

This patch defines the stream-ids for Chassis-2 devices. DPAA1 is
reserved for future use.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-lsch3: Rewrite comment for stream IDs

LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared
same stream-id partitioning. This patch rewords the definition to
support all the

armv8: fsl-lsch3: Rewrite comment for stream IDs

LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared
same stream-id partitioning. This patch rewords the definition to
support all these SOCs.

Also have changes in description about iommu-map property updates
in PCI node.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h

The stream ID allocation for Chasis 3.0 devices can be shared among
LS1088, LS2088 and LS2080.

Signed-off-by: Bharat Bhushan <Bhara

armv8: fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h

The stream ID allocation for Chasis 3.0 devices can be shared among
LS1088, LS2088 and LS2080.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding

SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.

So Avoid RCWSR28 register hard-coding.

armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding

SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.

So Avoid RCWSR28 register hard-coding.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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arm: fsl-layerscape: Move QSGMII wriop_init to SoC file

MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.

So move QSGMII wriop_init_dpmac() to SoC file.

Signed-off-by: Prabhaka

arm: fsl-layerscape: Move QSGMII wriop_init to SoC file

MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.

So move QSGMII wriop_init_dpmac() to SoC file.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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fsl: Secure Boot: Enable IE (Key extention) Feature

For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a verified table of public
keys can b

fsl: Secure Boot: Enable IE (Key extention) Feature

For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a verified table of public
keys can be used. The latter feature is called IE Key Extension
Feature.

For Layerscape Chasis 3 based platforms, IE table is validated by
Bootrom and address of this table is written in scratch registers 13
and 14 via PBI commands.

Following are the steps describing usage of this feature:

1) Verify IE Table in ISBC phase using keys stored in fuses.
2) Install IE table. (To be used across verification of multiple
images stored in a static global structure.)
3) Use keys from IE table, to verify further images.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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fsl-layerscape/ppa: cleanup ppa.h

Moved the ifdef into ppa.h and removed the duplicated macros.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

armv8: lsch3: SECURE_BOOT: Define CONFIG_SYS_LS_PPA_ESBC_ADDR for LS2080A

Add header address for PPA to be validated during ESBC phase for LS2080A
platform based on Layescape Chasis 3.

Signed-off-b

armv8: lsch3: SECURE_BOOT: Define CONFIG_SYS_LS_PPA_ESBC_ADDR for LS2080A

Add header address for PPA to be validated during ESBC phase for LS2080A
platform based on Layescape Chasis 3.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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i2c: lpc32xx: Move definitions to header file

Since the lpc32xx i2c driver does not yet support the devicetree bindings,
this structure is also needed by the board file as the hardware description
i

i2c: lpc32xx: Move definitions to header file

Since the lpc32xx i2c driver does not yet support the devicetree bindings,
this structure is also needed by the board file as the hardware description
is done there.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>

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ti: common: board_detect: Rename EEPROM scratch start macro

Non OMAP platforms i.e. Keystone will also need to use the board
EEPROM helpers so let's make the macro platform independent.

Signed-off-

ti: common: board_detect: Rename EEPROM scratch start macro

Non OMAP platforms i.e. Keystone will also need to use the board
EEPROM helpers so let's make the macro platform independent.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

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ARM: OMAP5+: GPIO: Add GPIO_TO_PIN() macro

GPIO_TO_PIN(bank, bank_gpio) returns the GPIO index
from the GPIO bank number and bank's GPIO offset number.

Signed-off-by: Roger Quadros <rogerq@ti.com>

ARM: OMAP5+: GPIO: Add GPIO_TO_PIN() macro

GPIO_TO_PIN(bank, bank_gpio) returns the GPIO index
from the GPIO bank number and bank's GPIO offset number.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
configs/bk4r1_defconfig
configs/colibri_vf_defconfig
configs/pcm052_defconfig
i

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
configs/bk4r1_defconfig
configs/colibri_vf_defconfig
configs/pcm052_defconfig
include/configs/colibri_vf.h
include/configs/pcm052.h

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arm: i.MX6UL: add Armadeus Systems OPOS6UL SoM and OPOS6ULDev carrier board

OPOS6UL is an i.MX6UL based SoM with 256MB RAM, 4GB eMMC and an ethernet
phy. OPOS6ULDev is carrier board for the OPOS6UL.

arm: i.MX6UL: add Armadeus Systems OPOS6UL SoM and OPOS6ULDev carrier board

OPOS6UL is an i.MX6UL based SoM with 256MB RAM, 4GB eMMC and an ethernet
phy. OPOS6ULDev is carrier board for the OPOS6UL.

U-Boot SPL 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09)
Trying to boot from MMC1

U-Boot 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09 +0100)

CPU: Freescale i.MX6UL rev1.0 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 40C
Reset cause: POR
Model: Armadeus Systems OPOS6UL SoM on OPOS6ULDev board
DRAM: 256 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Video: 800x480x18
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce SPL_SYS_THUMB_BUILD

Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
various reasons. We also have cases where we only

arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce SPL_SYS_THUMB_BUILD

Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
various reasons. We also have cases where we only build SPL in Thumb2 mode due
to size constraints and wish to build the rest of the system in ARM mode. So
in this migration we introduce a new symbol as well, SPL_SYS_THUMB_BUILD to
control if we build everything or just SPL (or in theory, just U-Boot) in
Thumb2 mode.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>

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Merge git://git.denx.de/u-boot-rockchip

This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang. Also included is SPL support for rk3399 and a fix for
rk3288 to get it bo

Merge git://git.denx.de/u-boot-rockchip

This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang. Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).

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arm: Update our 'ret' assembler macro slightly

We only support cores that do Thumb-1 or later. So we add a comment to
explain this and remove the architecture test.

Cc: Albert ARIBAUD <albert.u.bo

arm: Update our 'ret' assembler macro slightly

We only support cores that do Thumb-1 or later. So we add a comment to
explain this and remove the architecture test.

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Mans Rullgard <mans@mansr.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

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imx6: Add src_base structure define macro

Instead of initializing 'struct src' to SRC_BASE_ADDR on
every function better to have global define macro.

Reviewed by: Stefano Babic <sbabic@denx.de>
Sig

imx6: Add src_base structure define macro

Instead of initializing 'struct src' to SRC_BASE_ADDR on
every function better to have global define macro.

Reviewed by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@openedev.com>

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imx: Use IMX6_BMODE_* macros instead of numericals

Use meaningful macros IMX6_BMODE_*, instead of numerical
number in boot mode detection code.

Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Stef

imx: Use IMX6_BMODE_* macros instead of numericals

Use meaningful macros IMX6_BMODE_*, instead of numerical
number in boot mode detection code.

Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@openedev.com>

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