| aeadf065 | 09-Jul-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6: Adjust the GPR offset for mx6solox
On mx6solox there is an additional 0x4000 offset for the GPR registers.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <s
mx6: Adjust the GPR offset for mx6solox
On mx6solox there is an additional 0x4000 offset for the GPR registers.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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|
| 0a11d6f2 | 09-Jul-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6: Remove duplication of iomuxc structure
There is no need to keep iomuxc_base_regs structure as it serves the exact same
purpose of the iomuxc structure, which is to provide access to the GPR
reg
mx6: Remove duplication of iomuxc structure
There is no need to keep iomuxc_base_regs structure as it serves the exact same
purpose of the iomuxc structure, which is to provide access to the GPR
registers.
The additional fields of iomuxc_base_regs are not used. Other advantage of
'iomuxc' is that it has a shorter name and the variable declarations can fit
into a single line.
So remove iomuxc_base_regs structure and use iomuxc instead.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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|
| 8340e7ac | 23-Jun-2014 |
York Sun <yorksun@freescale.com> |
driver/ddr: Fix DDR4 driver for ARM
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.
Signed-off-by: York Sun <yorksun@freescale.com> |
| abce2c62 | 05-Jun-2014 |
Ian Campbell <ijc@hellion.org.uk> |
sunxi: add gpio driver
This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well
as providing the common gpio API (gpio_request/free, direction in/out, get/set
etc).
Signed-off-
sunxi: add gpio driver
This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well
as providing the common gpio API (gpio_request/free, direction in/out, get/set
etc).
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Henrik Nordström <henrik@henriknordstrom.net>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
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|
| 6620377e | 13-Jun-2014 |
Hans de Goede <hdegoede@redhat.com> |
sunxi: Add i2c support
Add support for the i2c controller found on all Allwinner sunxi SoCs,
this is the same controller as found on the Marvell orion5x and kirkwood
SoC families, with a slightly di
sunxi: Add i2c support
Add support for the i2c controller found on all Allwinner sunxi SoCs,
this is the same controller as found on the Marvell orion5x and kirkwood
SoC families, with a slightly different register layout, so this patch uses
the existing mvtwsi code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Heiko Schocher <hs@denx.de>
[ ijc -- updated u-boot-spl-fel.lds ]
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|
| 0db2bbdc | 13-Jun-2014 |
Hans de Goede <hdegoede@redhat.com> |
mvtwsi: convert to CONFIG_SYS_I2C framework
Note this has only been tested on Allwinner sunxi devices (support for which
gets introduced by a later patch).
The kirkwood changes have been compile te
mvtwsi: convert to CONFIG_SYS_I2C framework
Note this has only been tested on Allwinner sunxi devices (support for which
gets introduced by a later patch).
The kirkwood changes have been compile tested using the wireless_space board
config, the orion5x changes have been compile tested using the edminiv2 board
config.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Heiko Schocher <hs@denx.de>
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|
| dab5e346 | 16-Jul-2014 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
Conflicts:
boards.cfg |
| 84f24ac8 | 11-Jul-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx |
| f5860404 | 24-Jun-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6sx: Add pin definitions
Add the pin definitions for mx6sx.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
| 05d54b82 | 24-Jun-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6: Add support for the mx6solox variant
mx6solox is the newest member of the mx6 family.
Some of the new features on this variants are:
- Cortex M4 microcontroller (besides the CortexA9)
- Dual G
mx6: Add support for the mx6solox variant
mx6solox is the newest member of the mx6 family.
Some of the new features on this variants are:
- Cortex M4 microcontroller (besides the CortexA9)
- Dual Gigabit Ethernet
Add the initial support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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|
| e153333e | 09-Jul-2014 |
Eric Nelson <eric.nelson@boundarydevices.com> |
i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10
The pad settings for DISP0_DATA02 and DISP0_DAT10 were not
set in the same way as DISP0_DAT00-23, causing much flicker
in parallel RGB dis
i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10
The pad settings for DISP0_DATA02 and DISP0_DAT10 were not
set in the same way as DISP0_DAT00-23, causing much flicker
in parallel RGB displays on Dual-Lite and Solo processors.
These settings now match the i.MX6 Dual and Quad core versions.
Note that this fixes a regression in commit b47abc3 and that
this is the second time we've had a regression on these two
pads (See commit e654ddf).
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
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|
| 5ba95541 | 23-Jun-2014 |
Felipe Balbi <balbi@ti.com> |
usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x
Newer AM437x silicon requires us to explicitly power up
the USB2 PHY. By implementing usb_phy_power() we can
achieve that.
Signed-off-by
usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x
Newer AM437x silicon requires us to explicitly power up
the USB2 PHY. By implementing usb_phy_power() we can
achieve that.
Signed-off-by: Felipe Balbi <balbi@ti.com>
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|
| 8038b497 | 27-Jun-2014 |
Cooper Jr., Franklin <fcooper@ti.com> |
am43xx: Tune the system to avoid DSS underflows
* This is done by limiting the ARM's bandwidth and setting DSS priority in
the EMIF controller to ensure underflows do not occur. |
| 2c952111 | 27-Jun-2014 |
Franklin S. Cooper Jr <fcooper@ti.com> |
am43xx: Update EMIF DDR3 Configuration for AM43x GP
* Boot failures have been discovered due to a combination of routing issues and
non optimal ddr3 timings in the EMIF
* Since ddr3 timings are di
am43xx: Update EMIF DDR3 Configuration for AM43x GP
* Boot failures have been discovered due to a combination of routing issues and
non optimal ddr3 timings in the EMIF
* Since ddr3 timings are different after significant board layout changes
different timings are required for alpha, beta and production boards.
Signed-off-by: Franklin S. Cooper Jr <fcooper@ti.com>
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|
| 6ee3d00d | 07-Jul-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-i2c |
| c7e79dec | 09-Jun-2014 |
Hans de Goede <hdegoede@redhat.com> |
sunxi: Implement reset_cpu
There is no way to reset the cpu, so use the watchdog for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk> |
| fe0d9252 | 09-Jun-2014 |
Shaibal.Dutta <shaibal.dutta@broadcom.com> |
arm: Fix armv8 compilation error
Fix following compilation error when CONFIG_ARM64 is defined
Error: unknown or missing system register name at operand 2
-- `mrs x0,daifmsr daifset,#3'
Signed-off-
arm: Fix armv8 compilation error
Fix following compilation error when CONFIG_ARM64 is defined
Error: unknown or missing system register name at operand 2
-- `mrs x0,daifmsr daifset,#3'
Signed-off-by: Shaibal.Dutta <shaibal.dutta@broadcom.com>
Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Darwin Rambo <drambo@broadcom.com>
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|
| ed6c7f7f | 11-Jun-2014 |
Jeroen Hofstee <jeroen@myspectrum.nl> |
arm: spl: fix include guard
cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> |
| dc4d4aa1 | 10-Jun-2014 |
Chin Liang See <clsee@altera.com> |
socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See <clsee@a
socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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|
| 05b884b5 | 10-Jun-2014 |
Chin Liang See <clsee@altera.com> |
socfpga: Adding DesignWare watchdog support
To enable the DesignWare watchdog support at SOCFPGA
Cyclone V dev kit.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Anatolij Gustschin <agust@de
socfpga: Adding DesignWare watchdog support
To enable the DesignWare watchdog support at SOCFPGA
Cyclone V dev kit.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
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|
| 7237d22b | 25-Jun-2014 |
Sergey Kostanbaev <sergey.kostanbaev@gmail.com> |
arm: ep9315: Return back Cirrus Logic EDB9315A board support
This patch returns back support for old ep93xx processors family
Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com>
Cc: albe
arm: ep9315: Return back Cirrus Logic EDB9315A board support
This patch returns back support for old ep93xx processors family
Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com>
Cc: albert.u.boot@aribaud.net
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|
| fcfddfd5 | 23-Jun-2014 |
Jeroen Hofstee <jeroen@myspectrum.nl> |
ARM: cache_v7: use __weak
This is not only more readable but also prevents a warning
about a missing prototype. The prototypes which are actually
missing are added.
cc: Albert Aribaud <albert.u.boo
ARM: cache_v7: use __weak
This is not only more readable but also prevents a warning
about a missing prototype. The prototypes which are actually
missing are added.
cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@ti.com>
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|
| f749db3a | 23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support
LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as t
ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support
LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as the console
IFC timing is tightened for speedy booting
Support DDR3 and DDR4 as separated targets
Management Complex (MC) is enabled
Support for GIC 500 (based on GICv3 arch)
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
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|
| 2f78eae5 | 23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map an
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
show more ...
|
| 22932ffc | 23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8: Adjust MMU setup
Make MMU function reusable. Platform code can setup its own MMU tables.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn> |