1 /* 2 * (C) Copyright 2013 3 * David Feng <fenghua@phytium.com.cn> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/system.h> 10 #include <asm/armv8/mmu.h> 11 12 DECLARE_GLOBAL_DATA_PTR; 13 14 #ifndef CONFIG_SYS_DCACHE_OFF 15 void set_pgtable_section(u64 *page_table, u64 index, u64 section, 16 u64 memory_type) 17 { 18 u64 value; 19 20 value = section | PMD_TYPE_SECT | PMD_SECT_AF; 21 value |= PMD_ATTRINDX(memory_type); 22 page_table[index] = value; 23 } 24 25 /* to activate the MMU we need to set up virtual memory */ 26 static void mmu_setup(void) 27 { 28 int i, j, el; 29 bd_t *bd = gd->bd; 30 u64 *page_table = (u64 *)gd->arch.tlb_addr; 31 32 /* Setup an identity-mapping for all spaces */ 33 for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { 34 set_pgtable_section(page_table, i, i << SECTION_SHIFT, 35 MT_DEVICE_NGNRNE); 36 } 37 38 /* Setup an identity-mapping for all RAM space */ 39 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 40 ulong start = bd->bi_dram[i].start; 41 ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size; 42 for (j = start >> SECTION_SHIFT; 43 j < end >> SECTION_SHIFT; j++) { 44 set_pgtable_section(page_table, j, j << SECTION_SHIFT, 45 MT_NORMAL); 46 } 47 } 48 49 /* load TTBR0 */ 50 el = current_el(); 51 if (el == 1) { 52 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, 53 TCR_FLAGS | TCR_EL1_IPS_BITS, 54 MEMORY_ATTRIBUTES); 55 } else if (el == 2) { 56 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, 57 TCR_FLAGS | TCR_EL2_IPS_BITS, 58 MEMORY_ATTRIBUTES); 59 } else { 60 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, 61 TCR_FLAGS | TCR_EL3_IPS_BITS, 62 MEMORY_ATTRIBUTES); 63 } 64 /* enable the mmu */ 65 set_sctlr(get_sctlr() | CR_M); 66 } 67 68 /* 69 * Performs a invalidation of the entire data cache at all levels 70 */ 71 void invalidate_dcache_all(void) 72 { 73 __asm_invalidate_dcache_all(); 74 } 75 76 /* 77 * Performs a clean & invalidation of the entire data cache at all levels 78 */ 79 void flush_dcache_all(void) 80 { 81 __asm_flush_dcache_all(); 82 } 83 84 /* 85 * Invalidates range in all levels of D-cache/unified cache 86 */ 87 void invalidate_dcache_range(unsigned long start, unsigned long stop) 88 { 89 __asm_flush_dcache_range(start, stop); 90 } 91 92 /* 93 * Flush range(clean & invalidate) from all levels of D-cache/unified cache 94 */ 95 void flush_dcache_range(unsigned long start, unsigned long stop) 96 { 97 __asm_flush_dcache_range(start, stop); 98 } 99 100 void dcache_enable(void) 101 { 102 /* The data cache is not active unless the mmu is enabled */ 103 if (!(get_sctlr() & CR_M)) { 104 invalidate_dcache_all(); 105 __asm_invalidate_tlb_all(); 106 mmu_setup(); 107 } 108 109 set_sctlr(get_sctlr() | CR_C); 110 } 111 112 void dcache_disable(void) 113 { 114 uint32_t sctlr; 115 116 sctlr = get_sctlr(); 117 118 /* if cache isn't enabled no need to disable */ 119 if (!(sctlr & CR_C)) 120 return; 121 122 set_sctlr(sctlr & ~(CR_C|CR_M)); 123 124 flush_dcache_all(); 125 __asm_invalidate_tlb_all(); 126 } 127 128 int dcache_status(void) 129 { 130 return (get_sctlr() & CR_C) != 0; 131 } 132 133 #else /* CONFIG_SYS_DCACHE_OFF */ 134 135 void invalidate_dcache_all(void) 136 { 137 } 138 139 void flush_dcache_all(void) 140 { 141 } 142 143 void invalidate_dcache_range(unsigned long start, unsigned long stop) 144 { 145 } 146 147 void flush_dcache_range(unsigned long start, unsigned long stop) 148 { 149 } 150 151 void dcache_enable(void) 152 { 153 } 154 155 void dcache_disable(void) 156 { 157 } 158 159 int dcache_status(void) 160 { 161 return 0; 162 } 163 164 #endif /* CONFIG_SYS_DCACHE_OFF */ 165 166 #ifndef CONFIG_SYS_ICACHE_OFF 167 168 void icache_enable(void) 169 { 170 __asm_invalidate_icache_all(); 171 set_sctlr(get_sctlr() | CR_I); 172 } 173 174 void icache_disable(void) 175 { 176 set_sctlr(get_sctlr() & ~CR_I); 177 } 178 179 int icache_status(void) 180 { 181 return (get_sctlr() & CR_I) != 0; 182 } 183 184 void invalidate_icache_all(void) 185 { 186 __asm_invalidate_icache_all(); 187 } 188 189 #else /* CONFIG_SYS_ICACHE_OFF */ 190 191 void icache_enable(void) 192 { 193 } 194 195 void icache_disable(void) 196 { 197 } 198 199 int icache_status(void) 200 { 201 return 0; 202 } 203 204 void invalidate_icache_all(void) 205 { 206 } 207 208 #endif /* CONFIG_SYS_ICACHE_OFF */ 209 210 /* 211 * Enable dCache & iCache, whether cache is actually enabled 212 * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF 213 */ 214 void enable_caches(void) 215 { 216 icache_enable(); 217 dcache_enable(); 218 } 219 220 /* 221 * Flush range from all levels of d-cache/unified-cache 222 */ 223 void flush_cache(unsigned long start, unsigned long size) 224 { 225 flush_dcache_range(start, start + size); 226 } 227