| a033171b | 16-Feb-2015 |
Stephen Warren <swarren@wwwdotorg.org> |
bcm2835/rpi: add SPDX license tags for some files
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> |
| dc7de222 | 20-Feb-2015 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
ARM: keystone: move SoC headers to mach-keystone/include/mach
Move arch/arm/include/asm/arch-keystone/* -> arch/arm/mach-keystone/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panaso
ARM: keystone: move SoC headers to mach-keystone/include/mach
Move arch/arm/include/asm/arch-keystone/* -> arch/arm/mach-keystone/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com>
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| fd697ecf | 20-Feb-2015 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
ARM: orion5x: move SoC headers to mach-orion5x/include/mach
Move arch/arm/include/asm/arch-orion5x/* -> arch/arm/mach-orion5x/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.
ARM: orion5x: move SoC headers to mach-orion5x/include/mach
Move arch/arm/include/asm/arch-orion5x/* -> arch/arm/mach-orion5x/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
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| 5d0e6b28 | 20-Feb-2015 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
ARM: nomadik: move SoC headers to mach-nomadik/include/mach
Move arch/arm/include/asm/arch-nomadik/* -> arch/arm/mach-nomadik/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.
ARM: nomadik: move SoC headers to mach-nomadik/include/mach
Move arch/arm/include/asm/arch-nomadik/* -> arch/arm/mach-nomadik/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com> Cc: Alessandro Rubini <rubini@unipv.it>
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| ea385723 | 20-Feb-2015 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
ARM: kirkwood: move SoC headers to mach-kirkwood/include/mach
Move arch/arm/include/asm/arch-kirkwood/* -> arch/arm/mach-kirkwood/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panaso
ARM: kirkwood: move SoC headers to mach-kirkwood/include/mach
Move arch/arm/include/asm/arch-kirkwood/* -> arch/arm/mach-kirkwood/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
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| 3d357619 | 20-Feb-2015 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
ARM: davinci: move SoC headers to mach-davinci/include/mach
Move arch/arm/include/asm/arch-davinci/* -> arch/arm/mach-davinci/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.
ARM: davinci: move SoC headers to mach-davinci/include/mach
Move arch/arm/include/asm/arch-davinci/* -> arch/arm/mach-davinci/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com>
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| af930827 | 20-Feb-2015 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
ARM: at91: move SoC headers to mach-at91/include/mach
Move arch/arm/include/asm/arch-at91/* -> arch/arm/mach-at91/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-b
ARM: at91: move SoC headers to mach-at91/include/mach
Move arch/arm/include/asm/arch-at91/* -> arch/arm/mach-at91/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
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| a851604c | 16-Feb-2015 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of http://git.denx.de/u-boot-sunxi |
| 11c2e505 | 15-Feb-2015 |
Eric Nelson <eric.nelson@boundarydevices.com> |
ARM: i.MX: provide access to reset cause through get_imx_reset_cause()
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> |
| 1f516faa | 15-Jan-2015 |
Peng Fan <Peng.Fan@freescale.com> |
ARM: imx6: disable bandgap self-bias after boot
The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise
ARM: imx6: disable bandgap self-bias after boot
The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise performance of analog blocks. Also this bit should be disabled before the chip enters STOP mode or when ever the regular bandgap is disabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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| 0ce3f1f9 | 11-Feb-2015 |
Vladimir Zapolskiy <vz@mleia.com> |
ARM: lpc3250: config: add generic board support
The only LPC3250 board works fine with enabled generic board support, add CONFIG_SYS_GENERIC_BOARD right into the arch config header.
Signed-off-by:
ARM: lpc3250: config: add generic board support
The only LPC3250 board works fine with enabled generic board support, add CONFIG_SYS_GENERIC_BOARD right into the arch config header.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
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| 942cb0b6 | 07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
sunxi: Normalise FEL support
Make sunxi's FEL code fit with the normal U-Boot boot sequence instead of creating its own. There are some #ifdefs required in start.S. Future work will hopefully remove
sunxi: Normalise FEL support
Make sunxi's FEL code fit with the normal U-Boot boot sequence instead of creating its own. There are some #ifdefs required in start.S. Future work will hopefully remove these.
This series is available at u-boot-dm, branch sunxi-working.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| c01c71bc | 07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: spl: Provide for a board-specific loader
Some boards have a special way of loading U-Boot that does not fit with the existing SPL code. For example sunxi uses an 'FEL' mode where U-Boot is load
arm: spl: Provide for a board-specific loader
Some boards have a special way of loading U-Boot that does not fit with the existing SPL code. For example sunxi uses an 'FEL' mode where U-Boot is loaded over USB. Add a CONFIG option and boot mode for this.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| e11c6c27 | 07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code
The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch
arm: Allow lr to be saved by board code
The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link.
This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 51637afe | 04-Feb-2015 |
Hans de Goede <hdegoede@redhat.com> |
sunxi: dram: Un-inline dram helper functions
Move the dram helper functions to a separate C file, rather then having them as inline helpers in dram.h. This saves 144 bytes in the .text segment for s
sunxi: dram: Un-inline dram helper functions
Move the dram helper functions to a separate C file, rather then having them as inline helpers in dram.h. This saves 144 bytes in the .text segment for sun6i builds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| 66c98a0c | 11-Feb-2015 |
Vitaly Andrianov <vitalya@ti.com> |
keystone2: ddr3: eliminate using global ddr3_size variable
KS2 ddr3 initialization uses ddr3_size global variable before u-boot relocation. Even if the variable is not being used after relocation, w
keystone2: ddr3: eliminate using global ddr3_size variable
KS2 ddr3 initialization uses ddr3_size global variable before u-boot relocation. Even if the variable is not being used after relocation, writing to it corrupts relocation table.
This patch removes the global ddr3_size variable and uses local one instead.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Tested-by: Nishanth Menon <nm@ti.com>
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| bba379d4 | 11-Feb-2015 |
Steve Kipisz <s-kipisz2@ti.com> |
clock_am43xx:Set the MAC clock to /5 for OPP100
When EMAC is in the boot order, the boot ROM sets OPP50 and the MAC clock is set to /2. SPL needs to change it to /5 for Ethernet to generate the corr
clock_am43xx:Set the MAC clock to /5 for OPP100
When EMAC is in the boot order, the boot ROM sets OPP50 and the MAC clock is set to /2. SPL needs to change it to /5 for Ethernet to generate the correct txclk. This patch sets it correctly.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
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| 802bb57a | 16-Feb-2015 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as
ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| eca99c02 | 13-Feb-2015 |
Tom Rini <trini@ti.com> |
Merge git://git.denx.de/u-boot-samsung |
| ecdfb4e9 | 04-Feb-2015 |
Akshay Saraswat <akshay.s@samsung.com> |
Exynos542x: Add and enable get_periph_rate support
We planned to fetch peripheral rate through one generic API per peripheral. These generic peripheral functions are in turn expected to fetch apt va
Exynos542x: Add and enable get_periph_rate support
We planned to fetch peripheral rate through one generic API per peripheral. These generic peripheral functions are in turn expected to fetch apt values from a function refactored as per SoC versions. This patch adds support for fetching peripheral rates for Exynos5420 and Exynos5800.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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| 757fe635 | 11-Feb-2015 |
Simon Glass <sjg@chromium.org> |
dm: at91: Drop use of ATMEL_PIO_PORTS in the header file
With driver model the number of PIO ports is defined by platform data, so remove it from the header file.
Signed-off-by: Simon Glass <sjg@ch
dm: at91: Drop use of ATMEL_PIO_PORTS in the header file
With driver model the number of PIO ports is defined by platform data, so remove it from the header file.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
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| c956662c | 10-Feb-2015 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-atmel |
| 307367ea | 10-Feb-2015 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx |
| 2d6286ab | 25-Jan-2015 |
Graeme Russ <gruss@tss-engineering.com> |
arm: mxs: Add 'Wait for JTAG user' if booted in JTAG mode
When booting in JTAG mode, there is no way to use soft break-points, and no way of knowing when SPL has finished executing (so the user can
arm: mxs: Add 'Wait for JTAG user' if booted in JTAG mode
When booting in JTAG mode, there is no way to use soft break-points, and no way of knowing when SPL has finished executing (so the user can issue a 'halt' command to load u-boot.bin for example)
Add a debug output and simple loop to stop execution at the completion of the SPL initialisation as a pseudo break-point when booting in JTAG mode
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
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| e8cdeefc | 14-Jan-2015 |
Ye.Li <B37916@freescale.com> |
imx: mx6: Fixed AIPS3 base address issue
Should use AIPS3 configuration address 0x0227C000 to set AIPS3, not the AIPS3 base address. Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to ali
imx: mx6: Fixed AIPS3 base address issue
Should use AIPS3 configuration address 0x0227C000 to set AIPS3, not the AIPS3 base address. Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem.
Signed-off-by: Ye.Li <B37916@freescale.com>
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