armv8: fsl-layerscape: Fix early MMU table for nand boot

The early MMU table doesn't enable all addresses. Unused addresses
are marked as invalid, as introduced by commit 9979922. An entry
was missi

armv8: fsl-layerscape: Fix early MMU table for nand boot

The early MMU table doesn't enable all addresses. Unused addresses
are marked as invalid, as introduced by commit 9979922. An entry
was missing for NAND flash space, causing nand boot failure.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>

show more ...

armv8: ls2085a: Add workaround of errata A009635

If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because

armv8: ls2085a: Add workaround of errata A009635

If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.

Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

show more ...

armv8/layerscape: Update MMU table with execute-never bits

For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed

armv8/layerscape: Update MMU table with execute-never bits

For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reported-by: Zhichun Hua <zhichun.hua@freescale.com>

show more ...

drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3

Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one contr

drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3

Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun <yorksun@freescale.com>

show more ...

armv8/ls1043ardb: add USB support

Add support for the third USB controller for LS1043A.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls1043aqds: add LS1043AQDS board support

LS1043AQDS Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 DIMM
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND f

armv8/ls1043aqds: add LS1043AQDS board support

LS1043AQDS Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 DIMM
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card

Ethernet:
* Two RGMII ports
* XFI 10G port
* SGMII
* QSGMII with 4x 1G ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>

show more ...

pci/layerscape: add support for LS1043A PCIe LUT register access

The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definit

pci/layerscape: add support for LS1043A PCIe LUT register access

The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

show more ...

armv8: ls2085a: Add support of LS2085A SoC

Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.

Signed-off-by

armv8: ls2085a: Add support of LS2085A SoC

Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
Dropped #ifdef in cpu.h
Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>

show more ...

armv8: LS2080A: Rename LS2085A to reflect LS2080A

LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
S

armv8: LS2080A: Rename LS2085A to reflect LS2080A

LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>

show more ...

arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit

This patch addresses a problem mentioned recently on this mailing list:
[1].

In that posting a LS1021 based system was locking

arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit

This patch addresses a problem mentioned recently on this mailing list:
[1].

In that posting a LS1021 based system was locking up at about 5 minutes
after boot, but the problem was mysteriously related to the toolchain
used for building u-boot. Debugging the problem reveals a stuck
interrupt 29 on the GIC.

It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value. This causes the timer compare to fire 344 seconds
after u-boot configures it. Depending on how fast u-boot gets the
kernel booted, this amounts to about 5-minutes of Linux uptime before
locking up.

Apparently the bug is masked by some toolchains. Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
At any rate this patch makes the manipulation explicitly 64-bit which
alleviates the issue.

[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html

Signed-off-by: Chris Kilgour <techie@whiterocker.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

show more ...

arm: s5pc1xx: move SoC to mach-s5pc1xx

move arm/arm/cpu/armv7/s5pc1xx to arch/arm/mach-s5pc1xx

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

iomux-v3: Take MX6D in consideration for imx_iomux_v3_setup_pad()

We should also take MX6D option in consideration when defining
imx_iomux_v3_setup_pad().

Signed-off-by: Otavio Salvador <otavio@oss

iomux-v3: Take MX6D in consideration for imx_iomux_v3_setup_pad()

We should also take MX6D option in consideration when defining
imx_iomux_v3_setup_pad().

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>

show more ...

Merge branch 'master' of http://git.denx.de/u-boot-sunxi

sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3

The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz
on Allwinner H3 and using PLL6 as the clock source (PLL6/3).
This ca

sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3

The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz
on Allwinner H3 and using PLL6 as the clock source (PLL6/3).
This can be verified by reading the value of the AHB1_APB1_CFG_REG
register via /dev/mem. It always reads as 0x3180 regardless of
the current cpufreq operating point. So this configuration should
be safe for use in U-Boot too.

PLL6 also needs to be configured before it is used as the clock
source, according to the "CCU / Programming Guidelines" section
of the Allwinner manual.

The current low AHB1 clock speed is limiting the USB transfer
speed when booting via FEL. This patch can increase the FEL USB
transfer speed from ~510 KB/s to ~950 KB/s.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

show more ...

sunxi: Add H3 DRAM initialization support

Based on existing A23/A33 code and the original H3 boot0.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>

sunxi: Add H3 DRAM initialization support

Based on existing A23/A33 code and the original H3 boot0.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

show more ...

sunxi: Add basic H3 support

Add initial sun8i H3 support, only uart + mmc are supported for now.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Sig

sunxi: Add basic H3 support

Add initial sun8i H3 support, only uart + mmc are supported for now.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

show more ...

ns16550: move CONFIG_SYS_NS16550 to Kconfig

Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>

Merge branch 'master' of git://git.denx.de/u-boot-spi

spl: change return values of spl_*_load_image()

Make spl_*_load_image() functions return a value instead of
hanging if a problem is encountered. This enables main spl code
to make the decision wheth

spl: change return values of spl_*_load_image()

Make spl_*_load_image() functions return a value instead of
hanging if a problem is encountered. This enables main spl code
to make the decision whether to hang or not, thus preparing
it to support alternative boot devices.

Some boot devices (namely nand and spi) do not hang on error.
Instead, they return normally and SPL proceeds to boot the
contents of the load address. This is considered a bug and
is rectified by hanging on error for these devices as well.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans De Goede <hdegoede@redhat.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...

ARM: am43xx: Enable QUAD read and EDMA support for ti_qspi

Enable TI_EDMA3 and QUAD read support for ti_qspi on am43xx, this
increases read performance to 4 MB/s.

Signed-off-by: Vignesh R <vigneshr

ARM: am43xx: Enable QUAD read and EDMA support for ti_qspi

Enable TI_EDMA3 and QUAD read support for ti_qspi on am43xx, this
increases read performance to 4 MB/s.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

show more ...

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Merge branch 'master' of git://git.denx.de/u-boot-tegra

driver: gpio: hikey: Fix pointer conversion warnings for hikey

Fix below compilation warnings-
drivers/gpio/hi6220_gpio.c: In function ‘hi6220_gpio_probe’:
drivers/gpio/hi6220_gpio.c:82:15: warning:

driver: gpio: hikey: Fix pointer conversion warnings for hikey

Fix below compilation warnings-
drivers/gpio/hi6220_gpio.c: In function ‘hi6220_gpio_probe’:
drivers/gpio/hi6220_gpio.c:82:15: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
bank->base = (u8 *)plat->base;

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>

show more ...

video: mxsfb: introduce lcdif_power_down

Introudce a new function lcdif_power_down.

1. Waits for a VSYNC interrupt to guarantee the reset is done at the
VSYNC edge, which somehow makes the LCDIF

video: mxsfb: introduce lcdif_power_down

Introudce a new function lcdif_power_down.

1. Waits for a VSYNC interrupt to guarantee the reset is done at the
VSYNC edge, which somehow makes the LCDIF consume the display FIFO(?)
and helps the LCDIF work normally at the kernel stage.
2. Add power down function to stop lcdif.

The reason to introduce lcdif_power_down is that we want lcdif to be in
initial state when doing uboot reset or before kernel boot to make
system stable, otherwise system may hang.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>

show more ...

imx: mx6: add clock api for lcdif

Implement mxs_set_lcdclk, enable_lcdif_clock and enable_pll_video.
The three API can be used to configure lcdif related clock when
CONFIG_VIDEO_MXS enabled.

Signed

imx: mx6: add clock api for lcdif

Implement mxs_set_lcdclk, enable_lcdif_clock and enable_pll_video.
The three API can be used to configure lcdif related clock when
CONFIG_VIDEO_MXS enabled.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>

show more ...