1 /* 2 * Copyright (C) 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_COMMON_H 8 #define __LS2_COMMON_H 9 10 11 #define CONFIG_REMAKE_ELF 12 #define CONFIG_FSL_LAYERSCAPE 13 #define CONFIG_FSL_LSCH3 14 #define CONFIG_LS2080A 15 #define CONFIG_MP 16 #define CONFIG_GICV3 17 #define CONFIG_FSL_TZPC_BP147 18 19 /* Errata fixes */ 20 #define CONFIG_ARM_ERRATA_828024 21 #define CONFIG_ARM_ERRATA_826974 22 23 #include <asm/arch/ls2080a_stream_id.h> 24 #include <asm/arch/config.h> 25 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) 26 #define CONFIG_SYS_HAS_SERDES 27 #endif 28 29 /* Link Definitions */ 30 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 31 32 /* We need architecture specific misc initializations */ 33 #define CONFIG_ARCH_MISC_INIT 34 35 /* Link Definitions */ 36 #ifdef CONFIG_SPL 37 #define CONFIG_SYS_TEXT_BASE 0x80400000 38 #else 39 #define CONFIG_SYS_TEXT_BASE 0x30100000 40 #endif 41 42 #ifdef CONFIG_EMU 43 #define CONFIG_SYS_NO_FLASH 44 #endif 45 46 #define CONFIG_SUPPORT_RAW_INITRD 47 48 #define CONFIG_SKIP_LOWLEVEL_INIT 49 #define CONFIG_BOARD_EARLY_INIT_F 1 50 51 /* Flat Device Tree Definitions */ 52 #define CONFIG_OF_LIBFDT 53 #define CONFIG_OF_BOARD_SETUP 54 #define CONFIG_OF_STDOUT_VIA_ALIAS 55 56 /* new uImage format support */ 57 #define CONFIG_FIT 58 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 59 60 #ifndef CONFIG_SPL 61 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 62 #endif 63 #ifndef CONFIG_SYS_FSL_DDR4 64 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 65 #define CONFIG_SYS_DDR_RAW_TIMING 66 #endif 67 68 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 69 70 #define CONFIG_VERY_BIG_RAM 71 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 72 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 73 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 74 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 75 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 76 77 /* 78 * SMP Definitinos 79 */ 80 #define CPU_RELEASE_ADDR secondary_boot_func 81 82 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 83 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 84 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 85 /* 86 * DDR controller use 0 as the base address for binding. 87 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 88 */ 89 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 90 #define CONFIG_DP_DDR_CTRL 2 91 #define CONFIG_DP_DDR_NUM_CTRLS 1 92 #endif 93 94 /* Generic Timer Definitions */ 95 /* 96 * This is not an accurate number. It is used in start.S. The frequency 97 * will be udpated later when get_bus_freq(0) is available. 98 */ 99 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 100 101 /* Size of malloc() pool */ 102 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 103 104 /* I2C */ 105 #define CONFIG_CMD_I2C 106 #define CONFIG_SYS_I2C 107 #define CONFIG_SYS_I2C_MXC 108 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 109 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 110 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 111 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 112 113 /* Serial Port */ 114 #define CONFIG_CONS_INDEX 1 115 #define CONFIG_SYS_NS16550_SERIAL 116 #define CONFIG_SYS_NS16550_REG_SIZE 1 117 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 118 119 #define CONFIG_BAUDRATE 115200 120 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 121 122 /* IFC */ 123 #define CONFIG_FSL_IFC 124 125 /* 126 * During booting, IFC is mapped at the region of 0x30000000. 127 * But this region is limited to 256MB. To accommodate NOR, promjet 128 * and FPGA. This region is divided as below: 129 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 130 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 131 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 132 * 133 * To accommodate bigger NOR flash and other devices, we will map IFC 134 * chip selects to as below: 135 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 136 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 137 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 138 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 139 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 140 * 141 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 142 * CONFIG_SYS_FLASH_BASE has the final address (core view) 143 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 144 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 145 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 146 */ 147 148 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 149 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 150 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 151 152 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 153 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 154 155 #ifndef CONFIG_SYS_NO_FLASH 156 #define CONFIG_FLASH_CFI_DRIVER 157 #define CONFIG_SYS_FLASH_CFI 158 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 159 #define CONFIG_SYS_FLASH_QUIET_TEST 160 #endif 161 162 #ifndef __ASSEMBLY__ 163 unsigned long long get_qixis_addr(void); 164 #endif 165 #define QIXIS_BASE get_qixis_addr() 166 #define QIXIS_BASE_PHYS 0x20000000 167 #define QIXIS_BASE_PHYS_EARLY 0xC000000 168 #define QIXIS_STAT_PRES1 0xb 169 #define QIXIS_SDID_MASK 0x07 170 #define QIXIS_ESDHC_NO_ADAPTER 0x7 171 172 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 173 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 174 175 /* Debug Server firmware */ 176 #define CONFIG_FSL_DEBUG_SERVER 177 /* 2 sec timeout */ 178 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000) 179 180 /* MC firmware */ 181 #define CONFIG_FSL_MC_ENET 182 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 183 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 184 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 185 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 186 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 187 #ifndef CONFIG_LS2080A 188 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 189 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 190 #endif 191 192 /* 193 * Carve out a DDR region which will not be used by u-boot/Linux 194 * 195 * It will be used by MC and Debug Server. The MC region must be 196 * 512MB aligned, so the min size to hide is 512MB. 197 */ 198 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) 199 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) 200 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) 201 #define CONFIG_SYS_MEM_TOP_HIDE_MIN (512UL * 1024 * 1024) 202 #define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide() 203 #endif 204 205 /* PCIe */ 206 #define CONFIG_PCIE1 /* PCIE controler 1 */ 207 #define CONFIG_PCIE2 /* PCIE controler 2 */ 208 #define CONFIG_PCIE3 /* PCIE controler 3 */ 209 #define CONFIG_PCIE4 /* PCIE controler 4 */ 210 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 211 #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" 212 213 #define CONFIG_SYS_PCI_64BIT 214 215 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 216 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 217 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 218 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 219 220 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 221 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 222 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 223 224 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 225 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 226 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ 227 228 /* Command line configuration */ 229 #define CONFIG_CMD_CACHE 230 #define CONFIG_CMD_DHCP 231 #define CONFIG_CMD_ENV 232 #define CONFIG_CMD_GREPENV 233 #define CONFIG_CMD_MII 234 #define CONFIG_CMD_PING 235 236 /* Miscellaneous configurable options */ 237 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 238 #define CONFIG_ARCH_EARLY_INIT_R 239 240 /* Physical Memory Map */ 241 /* fixme: these need to be checked against the board */ 242 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 243 244 #define CONFIG_NR_DRAM_BANKS 3 245 246 #define CONFIG_HWCONFIG 247 #define HWCONFIG_BUFFER_SIZE 128 248 249 #define CONFIG_DISPLAY_CPUINFO 250 251 /* Initial environment variables */ 252 #define CONFIG_EXTRA_ENV_SETTINGS \ 253 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 254 "loadaddr=0x80100000\0" \ 255 "kernel_addr=0x100000\0" \ 256 "ramdisk_addr=0x800000\0" \ 257 "ramdisk_size=0x2000000\0" \ 258 "fdt_high=0xa0000000\0" \ 259 "initrd_high=0xffffffffffffffff\0" \ 260 "kernel_start=0x581200000\0" \ 261 "kernel_load=0xa0000000\0" \ 262 "kernel_size=0x2800000\0" \ 263 "console=ttyAMA0,38400n8\0" 264 265 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 266 "earlycon=uart8250,mmio,0x21c0500,115200 " \ 267 "ramdisk_size=0x2000000 default_hugepagesz=2m" \ 268 " hugepagesz=2m hugepages=16" 269 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 270 "$kernel_size && bootm $kernel_load" 271 #define CONFIG_BOOTDELAY 10 272 273 /* Monitor Command Prompt */ 274 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 275 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 276 sizeof(CONFIG_SYS_PROMPT) + 16) 277 #define CONFIG_SYS_HUSH_PARSER 278 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 279 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 280 #define CONFIG_SYS_LONGHELP 281 #define CONFIG_CMDLINE_EDITING 1 282 #define CONFIG_AUTO_COMPLETE 283 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 284 285 #ifndef __ASSEMBLY__ 286 unsigned long get_dram_size_to_hide(void); 287 #endif 288 289 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 290 291 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 292 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 293 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 294 #define CONFIG_SPL_ENV_SUPPORT 295 #define CONFIG_SPL_FRAMEWORK 296 #define CONFIG_SPL_I2C_SUPPORT 297 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 298 #define CONFIG_SPL_LIBCOMMON_SUPPORT 299 #define CONFIG_SPL_LIBGENERIC_SUPPORT 300 #define CONFIG_SPL_MAX_SIZE 0x16000 301 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 302 #define CONFIG_SPL_NAND_SUPPORT 303 #define CONFIG_SPL_SERIAL_SUPPORT 304 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 305 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 306 #define CONFIG_SPL_TEXT_BASE 0x1800a000 307 308 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 309 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 310 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 311 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 312 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 313 314 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 315 316 317 #endif /* __LS2_COMMON_H */ 318