| e6e3faa5 | 15-Dec-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq |
| 989c5f0a | 09-Dec-2015 |
Tang Yuantian <Yuantian.Tang@freescale.com> |
armv8: Add sata support on Layerscape ARMv8 board
Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This pa
armv8: Add sata support on Layerscape ARMv8 board
Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
show more ...
|
| 9711f528 | 08-Dec-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
armv8/ls1043ardb: add SECURE BOOT target for NOR
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is
armv8/ls1043ardb: add SECURE BOOT target for NOR
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
show more ...
|
| c107c0c0 | 04-Dec-2015 |
York Sun <yorksun@freescale.com> |
armv8: fsl-layerscape: Make DDR non secure in MMU tables
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU
armv8: fsl-layerscape: Make DDR non secure in MMU tables
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.
Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.
gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
Signed-off-by: York Sun <yorksun@freescale.com>
show more ...
|
| 6c4a1eba | 05-Dec-2015 |
Yao Yuan <yao.yuan@freescale.com> |
armv7/fsl-ls102xa: Workaround for DDR erratum A008514
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.
The value
armv7/fsl-ls102xa: Workaround for DDR erratum A008514
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.
The value: 63b2_0042h comes from the hardware team.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
show more ...
|
| 762b3535 | 05-Dec-2015 |
Yao Yuan <yao.yuan@freescale.com> |
arm: ls102xa: enable all the snoop signal for masters.
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for vari
arm: ls102xa: enable all the snoop signal for masters.
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
show more ...
|
| 7ba02618 | 05-Dec-2015 |
Yao Yuan <yao.yuan@freescale.com> |
arm: ls1021a: merge SoC specific code in a separate file
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksu
arm: ls1021a: merge SoC specific code in a separate file
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
show more ...
|
| e994dddb | 23-Nov-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8/ls1043ardb: Add support for >2GB memory
This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.H
armv8/ls1043ardb: Add support for >2GB memory
This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
show more ...
|
| 0c028a03 | 20-Nov-2015 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
arm: ls102x: add get_svr and IS_SVR_REV helper
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com> |
| 66562414 | 01-Dec-2015 |
Kamil Lulko <kamil.lulko@gmail.com> |
stm32: Convert serial driver to DM
Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org> |
| 81f50d93 | 28-Nov-2015 |
vishnupatekar <vishnupatekar0510@gmail.com> |
sunxi: Add support for Allwinner A83T DRAM
Add support for A83T dram. Register are different from sun8i A33.
init code is similar to A33 dram init.
hope we'll shift duplicate code in dram_sun8i_*
to
sunxi: Add support for Allwinner A83T DRAM
Add support for A83T dram. Register are different from sun8i A33.
init code is similar to A33 dram init.
hope we'll shift duplicate code in dram_sun8i_*
to dram helper in future.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
show more ...
|
| f542948b | 28-Nov-2015 |
vishnupatekar <vishnupatekar0510@gmail.com> |
sunxi: clk: add basic clocks for A83T
Add basic clocks pll1, pll5, and some default values from allwinner u-boot.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com] F
sunxi: clk: add basic clocks for A83T
Add basic clocks pll1, pll5, and some default values from allwinner u-boot.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz,
fixing the mmc support not working
[hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to
stabilize, fixing cold-booting directly from sdcard not working
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
show more ...
|
| d5a3357f | 28-Nov-2015 |
vishnupatekar <vishnupatekar0510@gmail.com> |
sunxi: Add support for UART0 in PB pin group on A83T
On A83T, PB9,PB10 are UART0 pins.
On allwinner A83T Dev board(h8homlet), this uart0 serial connector
is exposed.
Signed-off-by: Vishnu Patekar <
sunxi: Add support for UART0 in PB pin group on A83T
On A83T, PB9,PB10 are UART0 pins.
On allwinner A83T Dev board(h8homlet), this uart0 serial connector
is exposed.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
show more ...
|
| cbc1a91a | 20-Nov-2015 |
Hans de Goede <hdegoede@redhat.com> |
sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
According to the datasheets the max speed of AHB1 is 276 MHz, so
setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
and
sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
According to the datasheets the max speed of AHB1 is 276 MHz, so
setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
and gives us a nice speed-up in certain workloads.
Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Chen-Yu Tsai <wens@csie.org>
show more ...
|
| 0c890879 | 30-Nov-2015 |
Peng Fan <Peng.Fan@freescale.com> |
imx: mx6: fix reg base address when runtime usage
Should use parenthese to wrap the macro definition, otherwise
we will encounter error like the following:
"
if (base_addr != LCDIF1_BASE_ADDR) {
imx: mx6: fix reg base address when runtime usage
Should use parenthese to wrap the macro definition, otherwise
we will encounter error like the following:
"
if (base_addr != LCDIF1_BASE_ADDR) {
puts("Wrong LCD interface!\n");
return -EINVAL;
}
"
Without this patch, we will always encounter "Wrong LCD interface".
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
show more ...
|
| d9ae52c8 | 30-Nov-2015 |
Michal Simek <michal.simek@xilinx.com> |
zynq: sdhci: Move driver to DM
Move driver to DM
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org> |
| 769afa54 | 20-Nov-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM: zynq: Remove unused SERIAL macros for serial_zynq
Remove unused macros when driver was moved to DM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
| 5be93569 | 29-Nov-2015 |
Kamil Lulko <kamil.lulko@gmail.com> |
Change e-mail address of Kamil Lulko
Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com> |
| a85670e4 | 04-Dec-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx |
| 53c45f0c | 17-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: add rk3036 sdram driver
add rk3036 sdram driver so we can set up sdram in SPL
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org> |
| 07d8d35a | 17-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: add early uart driver
add early uart driver so we can print debug message in
SPL stage
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org> |
| c17736c0 | 17-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: rk3036: Add header files for GRF
GRF is the gereral register file. Add header files with register definitions.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chro
rockchip: rk3036: Add header files for GRF
GRF is the gereral register file. Add header files with register definitions.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 3f2ef139 | 17-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: rk3036: Add clock driver
Add a driver for setting up and modifying the various PLLs, peripheral
clocks and mmc clocks on RK3036
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simo
rockchip: rk3036: Add clock driver
Add a driver for setting up and modifying the various PLLs, peripheral
clocks and mmc clocks on RK3036
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| cc2244b8 | 17-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: add timer driver
some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.
Signed-off-by: Lin Huang <hl@rock-ch
rockchip: add timer driver
some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 1670c8c2 | 30-Nov-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq |