1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/processor.h> 11 #include <fsl_immap.h> 12 #include <fsl_ddr.h> 13 #include <fsl_errata.h> 14 15 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 16 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 17 { 18 int timeout = 1000; 19 20 ddr_out32(ptr, value); 21 22 while (ddr_in32(ptr) & bits) { 23 udelay(100); 24 timeout--; 25 } 26 if (timeout <= 0) 27 puts("Error: A007865 wait for clear timeout.\n"); 28 } 29 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */ 30 31 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 32 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 33 #endif 34 35 /* 36 * regs has the to-be-set values for DDR controller registers 37 * ctrl_num is the DDR controller number 38 * step: 0 goes through the initialization in one pass 39 * 1 sets registers and returns before enabling controller 40 * 2 resumes from step 1 and continues to initialize 41 * Dividing the initialization to two steps to deassert DDR reset signal 42 * to comply with JEDEC specs for RDIMMs. 43 */ 44 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 45 unsigned int ctrl_num, int step) 46 { 47 unsigned int i, bus_width; 48 struct ccsr_ddr __iomem *ddr; 49 u32 temp_sdram_cfg; 50 u32 total_gb_size_per_controller; 51 int timeout; 52 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 53 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 54 u32 *eddrtqcr1; 55 #endif 56 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 57 u32 temp32, mr6; 58 u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */ 59 u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ 60 u32 *vref_seq = vref_seq1; 61 #endif 62 #ifdef CONFIG_FSL_DDR_BIST 63 u32 mtcr, err_detect, err_sbe; 64 u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; 65 #endif 66 #ifdef CONFIG_FSL_DDR_BIST 67 char buffer[CONFIG_SYS_CBSIZE]; 68 #endif 69 70 switch (ctrl_num) { 71 case 0: 72 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 73 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 74 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 75 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 76 #endif 77 break; 78 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 79 case 1: 80 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 81 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 82 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 83 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 84 #endif 85 break; 86 #endif 87 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 88 case 2: 89 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 90 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 91 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 92 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 93 #endif 94 break; 95 #endif 96 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 97 case 3: 98 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 99 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 100 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 101 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800; 102 #endif 103 break; 104 #endif 105 default: 106 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 107 return; 108 } 109 110 if (step == 2) 111 goto step2; 112 113 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 114 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) 115 /* A008336 only applies to general DDR controllers */ 116 if ((ctrl_num == 0) || (ctrl_num == 1)) 117 #endif 118 ddr_out32(eddrtqcr1, 0x63b30002); 119 #endif 120 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 121 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) 122 /* A008514 only applies to DP-DDR controler */ 123 if (ctrl_num == 2) 124 #endif 125 ddr_out32(eddrtqcr1, 0x63b20002); 126 #endif 127 if (regs->ddr_eor) 128 ddr_out32(&ddr->eor, regs->ddr_eor); 129 130 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 131 132 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 133 if (i == 0) { 134 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); 135 ddr_out32(&ddr->cs0_config, regs->cs[i].config); 136 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); 137 138 } else if (i == 1) { 139 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); 140 ddr_out32(&ddr->cs1_config, regs->cs[i].config); 141 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); 142 143 } else if (i == 2) { 144 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); 145 ddr_out32(&ddr->cs2_config, regs->cs[i].config); 146 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); 147 148 } else if (i == 3) { 149 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); 150 ddr_out32(&ddr->cs3_config, regs->cs[i].config); 151 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); 152 } 153 } 154 155 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); 156 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); 157 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); 158 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); 159 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); 160 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); 161 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); 162 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); 163 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); 164 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); 165 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 166 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); 167 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); 168 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); 169 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); 170 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); 171 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); 172 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 173 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 174 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 175 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 176 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 177 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 178 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 179 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); 180 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); 181 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); 182 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); 183 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); 184 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); 185 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); 186 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); 187 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 188 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 189 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); 190 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 191 #ifndef CONFIG_SYS_FSL_DDR_EMU 192 /* 193 * Skip these two registers if running on emulator 194 * because emulator doesn't have skew between bytes. 195 */ 196 197 if (regs->ddr_wrlvl_cntl_2) 198 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 199 if (regs->ddr_wrlvl_cntl_3) 200 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 201 #endif 202 203 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 204 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 205 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 206 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); 207 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); 208 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); 209 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); 210 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); 211 #ifdef CONFIG_DEEP_SLEEP 212 if (is_warm_boot()) { 213 ddr_out32(&ddr->sdram_cfg_2, 214 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 215 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 216 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 217 218 /* DRAM VRef will not be trained */ 219 ddr_out32(&ddr->ddr_cdr2, 220 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 221 } else 222 #endif 223 { 224 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 225 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); 226 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 227 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); 228 } 229 ddr_out32(&ddr->err_disable, regs->err_disable); 230 ddr_out32(&ddr->err_int_en, regs->err_int_en); 231 for (i = 0; i < 32; i++) { 232 if (regs->debug[i]) { 233 debug("Write to debug_%d as %08x\n", 234 i+1, regs->debug[i]); 235 ddr_out32(&ddr->debug[i], regs->debug[i]); 236 } 237 } 238 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378 239 /* Erratum applies when accumulated ECC is used, or DBI is enabled */ 240 #define IS_ACC_ECC_EN(v) ((v) & 0x4) 241 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) 242 if (has_erratum_a008378()) { 243 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || 244 IS_DBI(regs->ddr_sdram_cfg_3)) 245 ddr_setbits32(&ddr->debug[28], 0x9 << 20); 246 } 247 #endif 248 249 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 250 /* Part 1 of 2 */ 251 /* This erraum only applies to verion 5.2.0 */ 252 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 253 /* Disable DRAM VRef training */ 254 ddr_out32(&ddr->ddr_cdr2, 255 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 256 /* Disable deskew */ 257 ddr_out32(&ddr->debug[28], 0x400); 258 /* Disable D_INIT */ 259 ddr_out32(&ddr->sdram_cfg_2, 260 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 261 ddr_out32(&ddr->debug[25], 0x9000); 262 } 263 #endif 264 /* 265 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 266 * deasserted. Clocks start when any chip select is enabled and clock 267 * control register is set. Because all DDR components are connected to 268 * one reset signal, this needs to be done in two steps. Step 1 is to 269 * get the clocks started. Step 2 resumes after reset signal is 270 * deasserted. 271 */ 272 if (step == 1) { 273 udelay(200); 274 return; 275 } 276 277 step2: 278 /* Set, but do not enable the memory */ 279 temp_sdram_cfg = regs->ddr_sdram_cfg; 280 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 281 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); 282 283 /* 284 * 500 painful micro-seconds must elapse between 285 * the DDR clock setup and the DDR config enable. 286 * DDR2 need 200 us, and DDR3 need 500 us from spec, 287 * we choose the max, that is 500 us for all of case. 288 */ 289 udelay(500); 290 mb(); 291 isb(); 292 293 #ifdef CONFIG_DEEP_SLEEP 294 if (is_warm_boot()) { 295 /* enter self-refresh */ 296 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 297 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 298 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 299 /* do board specific memory setup */ 300 board_mem_sleep_setup(); 301 302 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 303 } else 304 #endif 305 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 306 /* Let the controller go */ 307 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 308 mb(); 309 isb(); 310 311 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 312 /* Part 2 of 2 */ 313 /* This erraum only applies to verion 5.2.0 */ 314 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 315 /* Wait for idle */ 316 timeout = 40; 317 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 318 (timeout > 0)) { 319 udelay(1000); 320 timeout--; 321 } 322 if (timeout <= 0) { 323 printf("Controler %d timeout, debug_2 = %x\n", 324 ctrl_num, ddr_in32(&ddr->debug[1])); 325 } 326 327 /* The vref setting sequence is different for range 2 */ 328 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) 329 vref_seq = vref_seq2; 330 331 /* Set VREF */ 332 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 333 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 334 continue; 335 336 mr6 = (regs->ddr_sdram_mode_10 >> 16) | 337 MD_CNTL_MD_EN | 338 MD_CNTL_CS_SEL(i) | 339 MD_CNTL_MD_SEL(6) | 340 0x00200000; 341 temp32 = mr6 | vref_seq[0]; 342 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 343 temp32, MD_CNTL_MD_EN); 344 udelay(1); 345 debug("MR6 = 0x%08x\n", temp32); 346 temp32 = mr6 | vref_seq[1]; 347 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 348 temp32, MD_CNTL_MD_EN); 349 udelay(1); 350 debug("MR6 = 0x%08x\n", temp32); 351 temp32 = mr6 | vref_seq[2]; 352 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 353 temp32, MD_CNTL_MD_EN); 354 udelay(1); 355 debug("MR6 = 0x%08x\n", temp32); 356 } 357 ddr_out32(&ddr->sdram_md_cntl, 0); 358 ddr_out32(&ddr->debug[28], 0); /* Enable deskew */ 359 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ 360 /* wait for idle */ 361 timeout = 40; 362 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 363 (timeout > 0)) { 364 udelay(1000); 365 timeout--; 366 } 367 if (timeout <= 0) { 368 printf("Controler %d timeout, debug_2 = %x\n", 369 ctrl_num, ddr_in32(&ddr->debug[1])); 370 } 371 /* Restore D_INIT */ 372 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 373 } 374 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */ 375 376 total_gb_size_per_controller = 0; 377 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 378 if (!(regs->cs[i].config & 0x80000000)) 379 continue; 380 total_gb_size_per_controller += 1 << ( 381 ((regs->cs[i].config >> 14) & 0x3) + 2 + 382 ((regs->cs[i].config >> 8) & 0x7) + 12 + 383 ((regs->cs[i].config >> 4) & 0x3) + 0 + 384 ((regs->cs[i].config >> 0) & 0x7) + 8 + 385 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 386 26); /* minus 26 (count of 64M) */ 387 } 388 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 389 total_gb_size_per_controller *= 3; 390 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 391 total_gb_size_per_controller <<= 1; 392 /* 393 * total memory / bus width = transactions needed 394 * transactions needed / data rate = seconds 395 * to add plenty of buffer, double the time 396 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 397 * Let's wait for 800ms 398 */ 399 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) 400 >> SDRAM_CFG_DBW_SHIFT); 401 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 402 (get_ddr_freq(ctrl_num) >> 20)) << 2; 403 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 404 debug("total %d GB\n", total_gb_size_per_controller); 405 debug("Need to wait up to %d * 10ms\n", timeout); 406 407 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 408 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 409 (timeout >= 0)) { 410 udelay(10000); /* throttle polling rate */ 411 timeout--; 412 } 413 414 if (timeout <= 0) 415 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 416 #ifdef CONFIG_DEEP_SLEEP 417 if (is_warm_boot()) { 418 /* exit self-refresh */ 419 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 420 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 421 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 422 } 423 #endif 424 425 #ifdef CONFIG_FSL_DDR_BIST 426 #define BIST_PATTERN1 0xFFFFFFFF 427 #define BIST_PATTERN2 0x0 428 #define BIST_CR 0x80010000 429 #define BIST_CR_EN 0x80000000 430 #define BIST_CR_STAT 0x00000001 431 #define CTLR_INTLV_MASK 0x20000000 432 /* Perform build-in test on memory. Three-way interleaving is not yet 433 * supported by this code. */ 434 if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) { 435 puts("Running BIST test. This will take a while..."); 436 cs0_config = ddr_in32(&ddr->cs0_config); 437 cs0_bnds = ddr_in32(&ddr->cs0_bnds); 438 cs1_bnds = ddr_in32(&ddr->cs1_bnds); 439 cs2_bnds = ddr_in32(&ddr->cs2_bnds); 440 cs3_bnds = ddr_in32(&ddr->cs3_bnds); 441 if (cs0_config & CTLR_INTLV_MASK) { 442 /* set bnds to non-interleaving */ 443 ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); 444 ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); 445 ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); 446 ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); 447 } 448 ddr_out32(&ddr->mtp1, BIST_PATTERN1); 449 ddr_out32(&ddr->mtp2, BIST_PATTERN1); 450 ddr_out32(&ddr->mtp3, BIST_PATTERN2); 451 ddr_out32(&ddr->mtp4, BIST_PATTERN2); 452 ddr_out32(&ddr->mtp5, BIST_PATTERN1); 453 ddr_out32(&ddr->mtp6, BIST_PATTERN1); 454 ddr_out32(&ddr->mtp7, BIST_PATTERN2); 455 ddr_out32(&ddr->mtp8, BIST_PATTERN2); 456 ddr_out32(&ddr->mtp9, BIST_PATTERN1); 457 ddr_out32(&ddr->mtp10, BIST_PATTERN2); 458 mtcr = BIST_CR; 459 ddr_out32(&ddr->mtcr, mtcr); 460 timeout = 100; 461 while (timeout > 0 && (mtcr & BIST_CR_EN)) { 462 mdelay(1000); 463 timeout--; 464 mtcr = ddr_in32(&ddr->mtcr); 465 } 466 if (timeout <= 0) 467 puts("Timeout\n"); 468 else 469 puts("Done\n"); 470 err_detect = ddr_in32(&ddr->err_detect); 471 err_sbe = ddr_in32(&ddr->err_sbe); 472 if (mtcr & BIST_CR_STAT) { 473 printf("BIST test failed on controller %d.\n", 474 ctrl_num); 475 } 476 if (err_detect || (err_sbe & 0xffff)) { 477 printf("ECC error detected on controller %d.\n", 478 ctrl_num); 479 } 480 481 if (cs0_config & CTLR_INTLV_MASK) { 482 /* restore bnds registers */ 483 ddr_out32(&ddr->cs0_bnds, cs0_bnds); 484 ddr_out32(&ddr->cs1_bnds, cs1_bnds); 485 ddr_out32(&ddr->cs2_bnds, cs2_bnds); 486 ddr_out32(&ddr->cs3_bnds, cs3_bnds); 487 } 488 } 489 #endif 490 } 491