| e9024ef2 | 03-Feb-2014 |
Dan Murphy <dmurphy@ti.com> |
ARM: O5/dra7xx: Add SATA boot support
Add the SATA boot support for OMAP5 and dra7xx.
Renamed the omap_sata_init to the common init_sata(int dev)
for commonality in with sata stack.
Added the ROM
ARM: O5/dra7xx: Add SATA boot support
Add the SATA boot support for OMAP5 and dra7xx.
Renamed the omap_sata_init to the common init_sata(int dev)
for commonality in with sata stack.
Added the ROM boot device ID for SATA.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
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| e7538fee | 19-Feb-2014 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' |
| da781c60 | 12-Feb-2014 |
Andy Ng <andreas2025@gmail.com> |
imx6 SION bit has to be on for the pins that are used as ENET_REF_CLK
Signed-off-by: Andy Ng <andreas2025@gmail.com> |
| d7e269cf | 14-Jan-2014 |
Michal Simek <michal.simek@xilinx.com> |
zynq: Add support for U-BOOT SPL
SPL is using ps7_init.c/h files which are generated
from design tools which have to be copied to
boards/xilinx/zynq folder before compilation.
BSS section is moved
zynq: Add support for U-BOOT SPL
SPL is using ps7_init.c/h files which are generated
from design tools which have to be copied to
boards/xilinx/zynq folder before compilation.
BSS section is moved to SDRAM because fat support
requires more space than SRAM size.
Added:
- MMC and QSPI support
- Boot OS directly from SPL
- Enable SPL command
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
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| 97598fcf | 21-Nov-2013 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
net: zynq_gem: Calculate clock dividers dynamically
Remove hard coded clock divider setting and use the Zynq clock framework
to dynamically calculate appropriate dividers at run time.
Signed-off-by
net: zynq_gem: Calculate clock dividers dynamically
Remove hard coded clock divider setting and use the Zynq clock framework
to dynamically calculate appropriate dividers at run time.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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| 1cd46ed2 | 21-Nov-2013 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
net: zynq_gem: Move RCLK details out of driver
The GEM driver should not need to know about Zynq specific details of
RCLK related registers and bitfields in the SLCR. Move those details to
the slcr
net: zynq_gem: Move RCLK details out of driver
The GEM driver should not need to know about Zynq specific details of
RCLK related registers and bitfields in the SLCR. Move those details to
the slcr driver.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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| 6c3e61de | 21-Nov-2013 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
zynq: Provide a framework to read clock frequencies
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
| bf834950 | 19-Dec-2013 |
Michal Simek <michal.simek@xilinx.com> |
zynq: serial: Simplify serial driver initialization
Define both serial uarts in the driver and return
default uart based on board configuration.
- Move baseaddresses to hardware.h
- Define default
zynq: serial: Simplify serial driver initialization
Define both serial uarts in the driver and return
default uart based on board configuration.
- Move baseaddresses to hardware.h
- Define default baudrate and clock values
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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| 62798121 | 16-Jan-2014 |
Michal Simek <michal.simek@xilinx.com> |
zynq: Move bootmode to headers
These numbers will be reused by SPL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
| a87a0ce7 | 19-Feb-2014 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master' |
| b56e71e2 | 21-Dec-2013 |
Sourav Poddar <sourav.poddar@ti.com> |
am43xx: Add qspi support
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> |
| 060aaada | 17-Feb-2014 |
Markus Niebel <Markus.Niebel@tqs.de> |
spi: mxc_spi: i.MX6 DL/S have only 4 eCSPI controller
The dual lite and solo variant have only 4 SPI controller.
respect this in the MXC_SPI_BASE_ADRESSES macro
Signed-off-by: Markus Niebel <Markus
spi: mxc_spi: i.MX6 DL/S have only 4 eCSPI controller
The dual lite and solo variant have only 4 SPI controller.
respect this in the MXC_SPI_BASE_ADRESSES macro
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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| d7cbcc76 | 17-Feb-2014 |
Markus Niebel <Markus.Niebel@tq-group.de> |
spi: spi-mxc: add defines for clk inactive state for ECSPI
Provide define for the SCLK_CTL field of the config reg of ECSPI.
While at it, oder the defines to improve readability and make
adding more
spi: spi-mxc: add defines for clk inactive state for ECSPI
Provide define for the SCLK_CTL field of the config reg of ECSPI.
While at it, oder the defines to improve readability and make
adding more defines easier.
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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| c4d376fd | 17-Feb-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-arm |
| 5e77a745 | 06-Feb-2014 |
Stephen Warren <swarren@wwwdotorg.org> |
ARM: bcm2835: fix mbox POWER_STATE_RESP_ON value
Typo: The correct value is 1 not 2.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> |
| d53ccdb3 | 13-Feb-2014 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' |
| 17998eff | 11-Feb-2014 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-arm |
| 6d73c234 | 29-Jan-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6: Enable L2 cache support
Add L2 cache support and enable it by default.
Configure the L2 cache in the same way as done by FSL kernel:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git
mx6: Enable L2 cache support
Add L2 cache support and enable it by default.
Configure the L2 cache in the same way as done by FSL kernel:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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| 94db6655 | 26-Jan-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6: Distinguish mx6dual from mx6quad
Currently when we boot a mx6dual U-boot reports that it is a mx6quad.
Report it as MX6D instead:
CPU: Freescale i.MX6D rev1.2 at 792 MHz
Signed-off-by: Fab
mx6: Distinguish mx6dual from mx6quad
Currently when we boot a mx6dual U-boot reports that it is a mx6quad.
Report it as MX6D instead:
CPU: Freescale i.MX6D rev1.2 at 792 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
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| 6a99f03d | 26-Jan-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
imx: Introduce a header for the imx cpu versions
Instead of duplicating the CPU definitions at mx5 and mx6 sys_proto.h header
files, introduce a common header to centralize such definitions.
Signed
imx: Introduce a header for the imx cpu versions
Instead of duplicating the CPU definitions at mx5 and mx6 sys_proto.h header
files, introduce a common header to centralize such definitions.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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| d3e016cc | 05-Feb-2014 |
Rajeshwari S Shinde <rajeshwari.s@samsung.com> |
MMC: DWMMC: Correct the CLKDIV register value
This patch corrects the divider value written to CLKDIV register.
Since SDCLKIN is divided inside controller by the DIVRATIO value set
in the CLKSEL reg
MMC: DWMMC: Correct the CLKDIV register value
This patch corrects the divider value written to CLKDIV register.
Since SDCLKIN is divided inside controller by the DIVRATIO value set
in the CLKSEL register, we need to use the same output clock value to
calculate the CLKDIV value.
as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
Input parameter to mmc_clk is changed to dwmci_host, since
we need the same to read DWMCI_CLKSEL register.
This improves the read timing values for channel 0 on SMDK5250
from 0.288sec to 0.144sec
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
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| d1cbf0a5 | 22-Jan-2014 |
Piotr Wilczek <p.wilczek@samsung.com> |
arm:s5pc110: add cpu revision
This patch adds s5p_cpu_rev.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <
arm:s5pc110: add cpu revision
This patch adds s5p_cpu_rev.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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| 34991bbf | 22-Jan-2014 |
Piotr Wilczek <p.wilczek@samsung.com> |
arm:exynos: add cpu revision
This patch enables to read cpu revision on Exynos CPU.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Sig
arm:exynos: add cpu revision
This patch enables to read cpu revision on Exynos CPU.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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| c8d4b2f8 | 27-Jan-2014 |
Marek Vasut <marex@denx.de> |
ARM: IXP: Remove the IXP architecture support
The architecture is unmaintained and dead, remove it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Mic
ARM: IXP: Remove the IXP architecture support
The architecture is unmaintained and dead, remove it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michael Schwingen <michael@schwingen.org>
Cc: Tom Rini <trini@ti.com>
show more ...
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| 1501cc94 | 29-Jan-2014 |
Minkyu Kang <mk7.kang@samsung.com> |
exynos: pinmux: remove unnecessary define
The value of PERIPH_ID_COUNT was wrong, and unnecessary.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> |