Merge branch 'master' of git://git.denx.de/u-boot

Merge git://git.denx.de/u-boot-socfpga

arm: socfpga: enable data/inst prefetch and shared override in the L2

Update the L2 AUX CTRL settings for the SoCFPGA.

Enabling D and I prefetch bits helps improve SDRAM performance on the
platform

arm: socfpga: enable data/inst prefetch and shared override in the L2

Update the L2 AUX CTRL settings for the SoCFPGA.

Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.

Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

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mx6: Set shared override bit in PL310 AUX_CTRL register

Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Sh

mx6: Set shared override bit in PL310 AUX_CTRL register

Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

This was inspired by a patch from Catalin Marinas [1] and also from recent
discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring
suggested that bootloaders should initialize the cache.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html
[2] https://lkml.org/lkml/2015/2/20/199

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>

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Merge branch 'master' of git://git.denx.de/u-boot-arm

Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

mx6: Enable L2 cache support

Add L2 cache support and enable it by default.

Configure the L2 cache in the same way as done by FSL kernel:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git

mx6: Enable L2 cache support

Add L2 cache support and enable it by default.

Configure the L2 cache in the same way as done by FSL kernel:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>

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Merge git://git.denx.de/u-boot-arm

Conflicts:
board/freescale/mx6qsabrelite/Makefile
board/freescale/mx6qsabrelite/mx6qsabrelite.c
include/configs/mx6qsabrelite.h

Signed-off-by: Stefano Babic <s

Merge git://git.denx.de/u-boot-arm

Conflicts:
board/freescale/mx6qsabrelite/Makefile
board/freescale/mx6qsabrelite/mx6qsabrelite.c
include/configs/mx6qsabrelite.h

Signed-off-by: Stefano Babic <sbabic@denx.de>

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Merge branch 'u-boot/master' into u-boot-arm/master

Add GPL-2.0+ SPDX-License-Identifier to source files

Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>

armv7: add PL310 support to u-boot

PL310 is the L2$ controller from ARM used in many SoCs
including the Cortex-A9 based OMAP4430

Add support for some of the key PL310 operations
- Invalidate all

armv7: add PL310 support to u-boot

PL310 is the L2$ controller from ARM used in many SoCs
including the Cortex-A9 based OMAP4430

Add support for some of the key PL310 operations
- Invalidate all
- Invalidate range
- Flush(clean & invalidate) all
- Flush range

Signed-off-by: Aneesh V <aneesh@ti.com>

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